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    Searched refs:mmRLC_LB_INIT_CU_MASK (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1153 #define mmRLC_LB_INIT_CU_MASK 0x3107
gfx_7_0_d.h 1289 #define mmRLC_LB_INIT_CU_MASK 0x310f
gfx_7_2_d.h 1302 #define mmRLC_LB_INIT_CU_MASK 0x310f
gfx_8_0_d.h 1402 #define mmRLC_LB_INIT_CU_MASK 0xec4f
gfx_8_1_d.h 1402 #define mmRLC_LB_INIT_CU_MASK 0xec4f
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c 1730 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1732 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1779 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1781 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
amdgpu_gfx_v6_0.c 2547 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
amdgpu_gfx_v7_0.c 3554 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6054 #define mmRLC_LB_INIT_CU_MASK 0x4c4f
gc_9_1_offset.h 6276 #define mmRLC_LB_INIT_CU_MASK 0x4c4f
gc_9_2_1_offset.h 6252 #define mmRLC_LB_INIT_CU_MASK 0x4c4f

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