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    Searched refs:mmRLC_SERDES_WR_CTRL (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 2586 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2591 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2637 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2660 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
amdgpu_gfx_v7_0.c 3599 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3652 WREG32(mmRLC_SERDES_WR_CTRL, data);
3702 WREG32(mmRLC_SERDES_WR_CTRL, data);
amdgpu_gfx_v8_0.c 5507 data = RREG32(mmRLC_SERDES_WR_CTRL);
5535 WREG32(mmRLC_SERDES_WR_CTRL, data);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1173 #define mmRLC_SERDES_WR_CTRL 0x3117
gfx_7_0_d.h 1305 #define mmRLC_SERDES_WR_CTRL 0x311f
gfx_7_2_d.h 1318 #define mmRLC_SERDES_WR_CTRL 0x311f
gfx_8_0_d.h 1418 #define mmRLC_SERDES_WR_CTRL 0xec5f
gfx_8_1_d.h 1416 #define mmRLC_SERDES_WR_CTRL 0xec5f
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6082 #define mmRLC_SERDES_WR_CTRL 0x4c5f
gc_9_1_offset.h 6304 #define mmRLC_SERDES_WR_CTRL 0x4c5f
gc_9_2_1_offset.h 6282 #define mmRLC_SERDES_WR_CTRL 0x4c5f

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