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    Searched refs:mmSCRATCH_REG0 (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h 213 #define mmSCRATCH_REG0 0x2040
gc_9_0_offset.h 4638 #define mmSCRATCH_REG0 0x2040
gc_9_1_offset.h 4868 #define mmSCRATCH_REG0 0x2040
gc_9_2_1_offset.h 4824 #define mmSCRATCH_REG0 0x2040
gc_10_1_0_offset.h 7104 #define mmSCRATCH_REG0 0x2040
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
soc15_common.h 81 uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \
amdgpu_gfx_v6_0.c 1790 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
amdgpu_gfx_v10_0.c 421 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
amdgpu_gfx_v7_0.c 2080 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
amdgpu_gfx_v8_0.c 840 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
amdgpu_gfx_v9_0.c 941 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1183 #define mmSCRATCH_REG0 0x2140
gfx_7_0_d.h 406 #define mmSCRATCH_REG0 0xc040
gfx_7_2_d.h 418 #define mmSCRATCH_REG0 0xc040
gfx_8_0_d.h 456 #define mmSCRATCH_REG0 0xc040
gfx_8_1_d.h 456 #define mmSCRATCH_REG0 0xc040

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