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    Searched refs:mmSDMA0_CLK_CTRL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v3_0.c 89 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
102 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
120 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
127 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
141 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
155 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
170 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
184 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
1454 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1464 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data)
    [all...]
amdgpu_mxgpu_vi.c 97 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
228 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
249 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
amdgpu_cik_sdma.c 893 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
894 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
896 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
899 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
901 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
904 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
amdgpu_sdma_v4_0.c 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
257 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
2114 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2124 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2128 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2138 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2222 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
amdgpu_sdma_v5_0.c 1469 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1479 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1482 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1492 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1561 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
amdgpu_sdma_v2_4.c 75 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
82 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 68 #define mmSDMA0_CLK_CTRL 0x001b
sdma0_4_0_offset.h 70 #define mmSDMA0_CLK_CTRL 0x001b
sdma0_4_2_2_offset.h 70 #define mmSDMA0_CLK_CTRL 0x001b
sdma0_4_2_offset.h 70 #define mmSDMA0_CLK_CTRL 0x001b
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 162 #define mmSDMA0_CLK_CTRL 0x3403
oss_2_0_d.h 224 #define mmSDMA0_CLK_CTRL 0x3403
oss_3_0_1_d.h 159 #define mmSDMA0_CLK_CTRL 0x3403
oss_3_0_d.h 296 #define mmSDMA0_CLK_CTRL 0x3403
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 42 #define mmSDMA0_CLK_CTRL 0x001b
    [all...]

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