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    Searched refs:mmSDMA0_CNTL (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 1021 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1023 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1026 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1028 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1037 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1039 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1042 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1044 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
amdgpu_cik_sdma.c 382 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
397 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
1127 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1129 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1132 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1134 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1143 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1145 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1148 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1150 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl)
    [all...]
amdgpu_sdma_v3_0.c 592 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
611 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
1355 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1357 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1360 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1362 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1371 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1373 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1376 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1378 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl)
    [all...]
amdgpu_sdma_v4_0.c 1024 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1032 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1269 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1273 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1276 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1279 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1294 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1297 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1424 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1426 WREG32_SDMA(i, mmSDMA0_CNTL, temp)
    [all...]
amdgpu_sdma_v5_0.c 567 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
578 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
710 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
715 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
1400 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1401 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 70 #define mmSDMA0_CNTL 0x001c
sdma0_4_0_offset.h 72 #define mmSDMA0_CNTL 0x001c
sdma0_4_2_2_offset.h 72 #define mmSDMA0_CNTL 0x001c
sdma0_4_2_offset.h 72 #define mmSDMA0_CNTL 0x001c
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 163 #define mmSDMA0_CNTL 0x3404
oss_2_0_d.h 225 #define mmSDMA0_CNTL 0x3404
oss_3_0_1_d.h 160 #define mmSDMA0_CNTL 0x3404
oss_3_0_d.h 297 #define mmSDMA0_CNTL 0x3404
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 44 #define mmSDMA0_CNTL 0x001c
    [all...]

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