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    Searched refs:mmSDMA0_F32_CNTL (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 399 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
404 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
977 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
979 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
984 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
986 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
amdgpu_cik_sdma.c 420 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
425 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
1083 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1085 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1090 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1092 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
amdgpu_sdma_v5_0.c 602 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
604 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
732 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
734 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
amdgpu_sdma_v4_0.c 1058 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1060 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1430 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1432 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
amdgpu_sdma_v3_0.c 634 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
639 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 98 #define mmSDMA0_F32_CNTL 0x002a
sdma0_4_0_offset.h 100 #define mmSDMA0_F32_CNTL 0x002a
sdma0_4_2_2_offset.h 100 #define mmSDMA0_F32_CNTL 0x002a
sdma0_4_2_offset.h 100 #define mmSDMA0_F32_CNTL 0x002a
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 176 #define mmSDMA0_F32_CNTL 0x3412
oss_2_0_d.h 239 #define mmSDMA0_F32_CNTL 0x3412
oss_3_0_1_d.h 174 #define mmSDMA0_F32_CNTL 0x3412
oss_3_0_d.h 311 #define mmSDMA0_F32_CNTL 0x3412
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 72 #define mmSDMA0_F32_CNTL 0x002a
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