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    Searched refs:mmSDMA0_GFX_RB_BASE (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 208 #define mmSDMA0_GFX_RB_BASE 0x0081
sdma0_4_0_offset.h 212 #define mmSDMA0_GFX_RB_BASE 0x0081
sdma0_4_2_2_offset.h 212 #define mmSDMA0_GFX_RB_BASE 0x0081
sdma0_4_2_offset.h 208 #define mmSDMA0_GFX_RB_BASE 0x0081
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 190 #define mmSDMA0_GFX_RB_BASE 0x3481
oss_2_0_d.h 249 #define mmSDMA0_GFX_RB_BASE 0x3481
oss_3_0_1_d.h 217 #define mmSDMA0_GFX_RB_BASE 0x3481
oss_3_0_d.h 342 #define mmSDMA0_GFX_RB_BASE 0x3481
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 468 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
amdgpu_cik_sdma.c 489 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
amdgpu_sdma_v3_0.c 707 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
amdgpu_sdma_v5_0.c 674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
amdgpu_sdma_v4_0.c 1120 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 203 #define mmSDMA0_GFX_RB_BASE 0x0081
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