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    Searched refs:mmSDMA0_GFX_RB_BASE_HI (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 210 #define mmSDMA0_GFX_RB_BASE_HI 0x0082
sdma0_4_0_offset.h 214 #define mmSDMA0_GFX_RB_BASE_HI 0x0082
sdma0_4_2_2_offset.h 214 #define mmSDMA0_GFX_RB_BASE_HI 0x0082
sdma0_4_2_offset.h 210 #define mmSDMA0_GFX_RB_BASE_HI 0x0082
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 191 #define mmSDMA0_GFX_RB_BASE_HI 0x3482
oss_2_0_d.h 250 #define mmSDMA0_GFX_RB_BASE_HI 0x3482
oss_3_0_1_d.h 218 #define mmSDMA0_GFX_RB_BASE_HI 0x3482
oss_3_0_d.h 343 #define mmSDMA0_GFX_RB_BASE_HI 0x3482
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 469 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
amdgpu_cik_sdma.c 490 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
amdgpu_sdma_v3_0.c 708 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
amdgpu_sdma_v5_0.c 675 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
amdgpu_sdma_v4_0.c 1121 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 205 #define mmSDMA0_GFX_RB_BASE_HI 0x0082
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