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    Searched refs:mmSDMA0_GFX_RB_CNTL (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 357 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
359 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
445 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
452 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
476 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
amdgpu_cik_sdma.c 323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
325 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
473 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
496 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
amdgpu_sdma_v3_0.c 531 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
533 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
683 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
690 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
744 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
amdgpu_sdma_v5_0.c 505 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
507 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
637 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
644 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
739 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
amdgpu_sdma_v4_0.c 927 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
929 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1101 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1103 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1158 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 206 #define mmSDMA0_GFX_RB_CNTL 0x0080
sdma0_4_0_offset.h 210 #define mmSDMA0_GFX_RB_CNTL 0x0080
sdma0_4_2_2_offset.h 210 #define mmSDMA0_GFX_RB_CNTL 0x0080
sdma0_4_2_offset.h 206 #define mmSDMA0_GFX_RB_CNTL 0x0080
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 189 #define mmSDMA0_GFX_RB_CNTL 0x3480
oss_2_0_d.h 248 #define mmSDMA0_GFX_RB_CNTL 0x3480
oss_3_0_1_d.h 216 #define mmSDMA0_GFX_RB_CNTL 0x3480
oss_3_0_d.h 341 #define mmSDMA0_GFX_RB_CNTL 0x3480
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 201 #define mmSDMA0_GFX_RB_CNTL 0x0080
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