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    Searched refs:mmSDMA0_GFX_RB_RPTR_ADDR_LO (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 224 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
sdma0_4_0_offset.h 228 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
sdma0_4_2_2_offset.h 228 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
sdma0_4_2_offset.h 224 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 198 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
oss_2_0_d.h 257 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
oss_3_0_1_d.h 225 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
oss_3_0_d.h 350 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 463 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
amdgpu_sdma_v4_0.c 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
1114 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
amdgpu_cik_sdma.c 484 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
amdgpu_sdma_v3_0.c 702 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
amdgpu_sdma_v5_0.c 669 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 219 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
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