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    Searched refs:mmSDMA0_GFX_RB_WPTR (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 216 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
232 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
456 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
amdgpu_cik_sdma.c 188 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
202 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
477 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
493 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
amdgpu_sdma_v5_0.c 309 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
356 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
649 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
683 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
amdgpu_sdma_v3_0.c 378 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
405 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
731 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
amdgpu_sdma_v4_0.c 678 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
721 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
1108 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 216 #define mmSDMA0_GFX_RB_WPTR 0x0085
sdma0_4_0_offset.h 220 #define mmSDMA0_GFX_RB_WPTR 0x0085
sdma0_4_2_2_offset.h 220 #define mmSDMA0_GFX_RB_WPTR 0x0085
sdma0_4_2_offset.h 216 #define mmSDMA0_GFX_RB_WPTR 0x0085
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 193 #define mmSDMA0_GFX_RB_WPTR 0x3484
oss_2_0_d.h 252 #define mmSDMA0_GFX_RB_WPTR 0x3484
oss_3_0_1_d.h 220 #define mmSDMA0_GFX_RB_WPTR 0x3484
oss_3_0_d.h 345 #define mmSDMA0_GFX_RB_WPTR 0x3484
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 211 #define mmSDMA0_GFX_RB_WPTR 0x0085
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