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    Searched refs:mmSDMA0_PHASE0_QUANTUM (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 102 #define mmSDMA0_PHASE0_QUANTUM 0x002c
sdma0_4_0_offset.h 104 #define mmSDMA0_PHASE0_QUANTUM 0x002c
sdma0_4_2_2_offset.h 104 #define mmSDMA0_PHASE0_QUANTUM 0x002c
sdma0_4_2_offset.h 104 #define mmSDMA0_PHASE0_QUANTUM 0x002c
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 178 #define mmSDMA0_PHASE0_QUANTUM 0x3414
oss_2_0_d.h 241 #define mmSDMA0_PHASE0_QUANTUM 0x3414
oss_3_0_1_d.h 176 #define mmSDMA0_PHASE0_QUANTUM 0x3414
oss_3_0_d.h 313 #define mmSDMA0_PHASE0_QUANTUM 0x3414
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_sdma.c 387 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
amdgpu_sdma_v3_0.c 599 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
amdgpu_sdma_v5_0.c 571 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
amdgpu_sdma_v4_0.c 1028 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 76 #define mmSDMA0_PHASE0_QUANTUM 0x002c
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