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    Searched refs:mmSDMA0_PHASE1_QUANTUM (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 104 #define mmSDMA0_PHASE1_QUANTUM 0x002d
sdma0_4_0_offset.h 106 #define mmSDMA0_PHASE1_QUANTUM 0x002d
sdma0_4_2_2_offset.h 106 #define mmSDMA0_PHASE1_QUANTUM 0x002d
sdma0_4_2_offset.h 106 #define mmSDMA0_PHASE1_QUANTUM 0x002d
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 179 #define mmSDMA0_PHASE1_QUANTUM 0x3415
oss_2_0_d.h 242 #define mmSDMA0_PHASE1_QUANTUM 0x3415
oss_3_0_1_d.h 177 #define mmSDMA0_PHASE1_QUANTUM 0x3415
oss_3_0_d.h 314 #define mmSDMA0_PHASE1_QUANTUM 0x3415
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_sdma.c 389 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
amdgpu_sdma_v3_0.c 601 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
amdgpu_sdma_v5_0.c 573 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
amdgpu_sdma_v4_0.c 1029 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 78 #define mmSDMA0_PHASE1_QUANTUM 0x002d
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