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    Searched refs:mmSDMA0_POWER_CNTL (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_sdma.c 914 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
917 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
919 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
922 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
924 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
927 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
929 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
932 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
amdgpu_sdma_v4_0.c 101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
261 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
1288 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1291 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1300 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1307 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
2154 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2157 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2162 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
    [all...]
amdgpu_sdma_v3_0.c 157 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
177 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
1493 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1497 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1501 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1505 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1553 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
amdgpu_sdma_v5_0.c 1506 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1509 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1513 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1516 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1566 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 66 #define mmSDMA0_POWER_CNTL 0x001a
sdma0_4_0_offset.h 68 #define mmSDMA0_POWER_CNTL 0x001a
sdma0_4_2_2_offset.h 68 #define mmSDMA0_POWER_CNTL 0x001a
sdma0_4_2_offset.h 68 #define mmSDMA0_POWER_CNTL 0x001a
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 161 #define mmSDMA0_POWER_CNTL 0x3402
oss_2_0_d.h 223 #define mmSDMA0_POWER_CNTL 0x3402
oss_3_0_1_d.h 158 #define mmSDMA0_POWER_CNTL 0x3402
oss_3_0_d.h 295 #define mmSDMA0_POWER_CNTL 0x3402
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 40 #define mmSDMA0_POWER_CNTL 0x001a
    [all...]

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