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    Searched refs:mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 80 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
sdma0_4_0_offset.h 82 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
sdma0_4_2_2_offset.h 82 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
sdma0_4_2_offset.h 82 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 167 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
oss_2_0_d.h 230 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
oss_3_0_1_d.h 164 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
oss_3_0_d.h 301 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 441 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
amdgpu_cik_sdma.c 464 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
amdgpu_sdma_v3_0.c 679 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
amdgpu_sdma_v5_0.c 633 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
amdgpu_sdma_v4_0.c 1418 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 54 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
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