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    Searched refs:mmSPI_CONFIG_CNTL_1 (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_vi.c 139 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
amdgpu_gfx_v9_0.c 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
amdgpu_gfx_v10_0.c 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
amdgpu_gfx_v6_0.c 1748 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
amdgpu_gfx_v7_0.c 2023 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
amdgpu_gfx_v8_0.c 421 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1197 #define mmSPI_CONFIG_CNTL_1 0x244F
gfx_7_0_d.h 1480 #define mmSPI_CONFIG_CNTL_1 0x244f
gfx_7_2_d.h 1501 #define mmSPI_CONFIG_CNTL_1 0x244f
gfx_8_0_d.h 1693 #define mmSPI_CONFIG_CNTL_1 0x244f
gfx_8_1_d.h 1661 #define mmSPI_CONFIG_CNTL_1 0x244f
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 5136 #define mmSPI_CONFIG_CNTL_1 0x2441
gc_9_1_offset.h 5366 #define mmSPI_CONFIG_CNTL_1 0x2441
gc_9_2_1_offset.h 5324 #define mmSPI_CONFIG_CNTL_1 0x2441
gc_10_1_0_offset.h 2600 #define mmSPI_CONFIG_CNTL_1 0x11ef
    [all...]

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