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    Searched refs:mmSQ_CONFIG (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1415 #define mmSQ_CONFIG 0x2300
gfx_7_0_d.h 1787 #define mmSQ_CONFIG 0x2300
gfx_7_2_d.h 1808 #define mmSQ_CONFIG 0x2300
gfx_8_0_d.h 2001 #define mmSQ_CONFIG 0x2300
gfx_8_1_d.h 1969 #define mmSQ_CONFIG 0x2300
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v8_0.c 327 mmSQ_CONFIG, 0x07f80000, 0x01180000,
358 mmSQ_CONFIG, 0x07f80000, 0x01180000,
390 mmSQ_CONFIG, 0x07f80000, 0x07180000,
amdgpu_gfx_v9_0.c 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
2464 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
2467 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);
amdgpu_gfx_v7_0.c 2007 WREG32(mmSQ_CONFIG, 1);
2035 WREG32(mmSQ_CONFIG, 0);
amdgpu_gfx_v6_0.c 1757 WREG32(mmSQ_CONFIG, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 390 #define mmSQ_CONFIG 0x0300
gc_9_1_offset.h 384 #define mmSQ_CONFIG 0x0300
gc_9_2_1_offset.h 380 #define mmSQ_CONFIG 0x0300
gc_10_1_0_offset.h 2426 #define mmSQ_CONFIG 0x10a0
    [all...]

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