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Searched refs:mmUVD_DPG_PAUSE (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`1223 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1237 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1238 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1267 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1279 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1298 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1299 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1328 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);`
amdgpu_vcn_v2_0.c	`1150 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1161 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1164 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1193 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);`
amdgpu_vcn_v2_5.c	`1380 reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) & 1391 WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1394 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_DPG_PAUSE, 1422 WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`44 #define mmUVD_DPG_PAUSE 0x00d4`
vcn_2_0_0_offset.h	`402 #define mmUVD_DPG_PAUSE 0x0014`
vcn_2_5_offset.h	`417 #define mmUVD_DPG_PAUSE 0x0014`

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