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    Searched refs:mmUVD_JRBC_STATUS (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_jpeg_v2_5.c 207 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
446 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
463 SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
amdgpu_jpeg_v2_0.c 180 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
678 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
688 SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
amdgpu_jpeg_v1_0.c 341 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 288 #define mmUVD_JRBC_STATUS 0x051a
vcn_2_0_0_offset.h 138 #define mmUVD_JRBC_STATUS 0x0109
vcn_2_5_offset.h 153 #define mmUVD_JRBC_STATUS 0x0109

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