1 /* $NetBSD: amdgpu_jpeg_v1_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_jpeg_v1_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $"); 28 29 #include "amdgpu.h" 30 #include "amdgpu_jpeg.h" 31 #include "soc15.h" 32 #include "soc15d.h" 33 #include "vcn_v1_0.h" 34 35 #include "vcn/vcn_1_0_offset.h" 36 #include "vcn/vcn_1_0_sh_mask.h" 37 38 static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 39 static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev); 40 41 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) 42 { 43 struct amdgpu_device *adev = ring->adev; 44 ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); 45 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 46 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 47 ring->ring[(*ptr)++] = 0; 48 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); 49 } else { 50 ring->ring[(*ptr)++] = reg_offset; 51 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0); 52 } 53 ring->ring[(*ptr)++] = val; 54 } 55 56 static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr) 57 { 58 struct amdgpu_device *adev = ring->adev; 59 60 uint32_t reg, reg_offset, val, mask, i; 61 62 // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 63 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); 64 reg_offset = (reg << 2); 65 val = lower_32_bits(ring->gpu_addr); 66 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); 67 68 // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 69 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); 70 reg_offset = (reg << 2); 71 val = upper_32_bits(ring->gpu_addr); 72 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); 73 74 // 3rd to 5th: issue MEM_READ commands 75 for (i = 0; i <= 2; i++) { 76 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); 77 ring->ring[ptr++] = 0; 78 } 79 80 // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability 81 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); 82 reg_offset = (reg << 2); 83 val = 0x13; 84 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); 85 86 // 7th: program mmUVD_JRBC_RB_REF_DATA 87 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA); 88 reg_offset = (reg << 2); 89 val = 0x1; 90 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); 91 92 // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL 93 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); 94 reg_offset = (reg << 2); 95 val = 0x1; 96 mask = 0x1; 97 98 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0); 99 ring->ring[ptr++] = 0x01400200; 100 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0); 101 ring->ring[ptr++] = val; 102 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); 103 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 104 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 105 ring->ring[ptr++] = 0; 106 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3); 107 } else { 108 ring->ring[ptr++] = reg_offset; 109 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3); 110 } 111 ring->ring[ptr++] = mask; 112 113 //9th to 21st: insert no-op 114 for (i = 0; i <= 12; i++) { 115 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); 116 ring->ring[ptr++] = 0; 117 } 118 119 //22nd: reset mmUVD_JRBC_RB_RPTR 120 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR); 121 reg_offset = (reg << 2); 122 val = 0; 123 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); 124 125 //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch 126 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); 127 reg_offset = (reg << 2); 128 val = 0x12; 129 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); 130 } 131 132 /** 133 * jpeg_v1_0_decode_ring_get_rptr - get read pointer 134 * 135 * @ring: amdgpu_ring pointer 136 * 137 * Returns the current hardware read pointer 138 */ 139 static uint64_t jpeg_v1_0_decode_ring_get_rptr(struct amdgpu_ring *ring) 140 { 141 struct amdgpu_device *adev = ring->adev; 142 143 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 144 } 145 146 /** 147 * jpeg_v1_0_decode_ring_get_wptr - get write pointer 148 * 149 * @ring: amdgpu_ring pointer 150 * 151 * Returns the current hardware write pointer 152 */ 153 static uint64_t jpeg_v1_0_decode_ring_get_wptr(struct amdgpu_ring *ring) 154 { 155 struct amdgpu_device *adev = ring->adev; 156 157 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 158 } 159 160 /** 161 * jpeg_v1_0_decode_ring_set_wptr - set write pointer 162 * 163 * @ring: amdgpu_ring pointer 164 * 165 * Commits the write pointer to the hardware 166 */ 167 static void jpeg_v1_0_decode_ring_set_wptr(struct amdgpu_ring *ring) 168 { 169 struct amdgpu_device *adev = ring->adev; 170 171 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 172 } 173 174 /** 175 * jpeg_v1_0_decode_ring_insert_start - insert a start command 176 * 177 * @ring: amdgpu_ring pointer 178 * 179 * Write a start command to the ring. 180 */ 181 static void jpeg_v1_0_decode_ring_insert_start(struct amdgpu_ring *ring) 182 { 183 struct amdgpu_device *adev = ring->adev; 184 185 amdgpu_ring_write(ring, 186 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 187 amdgpu_ring_write(ring, 0x68e04); 188 189 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 190 amdgpu_ring_write(ring, 0x80010000); 191 } 192 193 /** 194 * jpeg_v1_0_decode_ring_insert_end - insert a end command 195 * 196 * @ring: amdgpu_ring pointer 197 * 198 * Write a end command to the ring. 199 */ 200 static void jpeg_v1_0_decode_ring_insert_end(struct amdgpu_ring *ring) 201 { 202 struct amdgpu_device *adev = ring->adev; 203 204 amdgpu_ring_write(ring, 205 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 206 amdgpu_ring_write(ring, 0x68e04); 207 208 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 209 amdgpu_ring_write(ring, 0x00010000); 210 } 211 212 /** 213 * jpeg_v1_0_decode_ring_emit_fence - emit an fence & trap command 214 * 215 * @ring: amdgpu_ring pointer 216 * @fence: fence to emit 217 * 218 * Write a fence and a trap command to the ring. 219 */ 220 static void jpeg_v1_0_decode_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 221 unsigned flags) 222 { 223 struct amdgpu_device *adev = ring->adev; 224 225 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 226 227 amdgpu_ring_write(ring, 228 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0)); 229 amdgpu_ring_write(ring, seq); 230 231 amdgpu_ring_write(ring, 232 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0)); 233 amdgpu_ring_write(ring, seq); 234 235 amdgpu_ring_write(ring, 236 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 237 amdgpu_ring_write(ring, lower_32_bits(addr)); 238 239 amdgpu_ring_write(ring, 240 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 241 amdgpu_ring_write(ring, upper_32_bits(addr)); 242 243 amdgpu_ring_write(ring, 244 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0)); 245 amdgpu_ring_write(ring, 0x8); 246 247 amdgpu_ring_write(ring, 248 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 249 amdgpu_ring_write(ring, 0); 250 251 amdgpu_ring_write(ring, 252 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 253 amdgpu_ring_write(ring, 0x01400200); 254 255 amdgpu_ring_write(ring, 256 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 257 amdgpu_ring_write(ring, seq); 258 259 amdgpu_ring_write(ring, 260 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 261 amdgpu_ring_write(ring, lower_32_bits(addr)); 262 263 amdgpu_ring_write(ring, 264 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 265 amdgpu_ring_write(ring, upper_32_bits(addr)); 266 267 amdgpu_ring_write(ring, 268 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2)); 269 amdgpu_ring_write(ring, 0xffffffff); 270 271 amdgpu_ring_write(ring, 272 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 273 amdgpu_ring_write(ring, 0x3fbc); 274 275 amdgpu_ring_write(ring, 276 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 277 amdgpu_ring_write(ring, 0x1); 278 279 /* emit trap */ 280 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 281 amdgpu_ring_write(ring, 0); 282 } 283 284 /** 285 * jpeg_v1_0_decode_ring_emit_ib - execute indirect buffer 286 * 287 * @ring: amdgpu_ring pointer 288 * @ib: indirect buffer to execute 289 * 290 * Write ring commands to execute the indirect buffer. 291 */ 292 static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring, 293 struct amdgpu_job *job, 294 struct amdgpu_ib *ib, 295 uint32_t flags) 296 { 297 struct amdgpu_device *adev = ring->adev; 298 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 299 300 amdgpu_ring_write(ring, 301 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0)); 302 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 303 304 amdgpu_ring_write(ring, 305 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0)); 306 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 307 308 amdgpu_ring_write(ring, 309 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 310 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 311 312 amdgpu_ring_write(ring, 313 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 314 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 315 316 amdgpu_ring_write(ring, 317 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0)); 318 amdgpu_ring_write(ring, ib->length_dw); 319 320 amdgpu_ring_write(ring, 321 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 322 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 323 324 amdgpu_ring_write(ring, 325 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 326 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 327 328 amdgpu_ring_write(ring, 329 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 330 amdgpu_ring_write(ring, 0); 331 332 amdgpu_ring_write(ring, 333 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 334 amdgpu_ring_write(ring, 0x01400200); 335 336 amdgpu_ring_write(ring, 337 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 338 amdgpu_ring_write(ring, 0x2); 339 340 amdgpu_ring_write(ring, 341 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 342 amdgpu_ring_write(ring, 0x2); 343 } 344 345 static void jpeg_v1_0_decode_ring_emit_reg_wait(struct amdgpu_ring *ring, 346 uint32_t reg, uint32_t val, 347 uint32_t mask) 348 { 349 struct amdgpu_device *adev = ring->adev; 350 uint32_t reg_offset = (reg << 2); 351 352 amdgpu_ring_write(ring, 353 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 354 amdgpu_ring_write(ring, 0x01400200); 355 356 amdgpu_ring_write(ring, 357 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 358 amdgpu_ring_write(ring, val); 359 360 amdgpu_ring_write(ring, 361 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 362 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 363 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 364 amdgpu_ring_write(ring, 0); 365 amdgpu_ring_write(ring, 366 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 367 } else { 368 amdgpu_ring_write(ring, reg_offset); 369 amdgpu_ring_write(ring, 370 PACKETJ(0, 0, 0, PACKETJ_TYPE3)); 371 } 372 amdgpu_ring_write(ring, mask); 373 } 374 375 static void jpeg_v1_0_decode_ring_emit_vm_flush(struct amdgpu_ring *ring, 376 unsigned vmid, uint64_t pd_addr) 377 { 378 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 379 uint32_t data0, data1, mask; 380 381 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 382 383 /* wait for register write */ 384 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 385 data1 = lower_32_bits(pd_addr); 386 mask = 0xffffffff; 387 jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask); 388 } 389 390 static void jpeg_v1_0_decode_ring_emit_wreg(struct amdgpu_ring *ring, 391 uint32_t reg, uint32_t val) 392 { 393 struct amdgpu_device *adev = ring->adev; 394 uint32_t reg_offset = (reg << 2); 395 396 amdgpu_ring_write(ring, 397 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 398 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 399 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 400 amdgpu_ring_write(ring, 0); 401 amdgpu_ring_write(ring, 402 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 403 } else { 404 amdgpu_ring_write(ring, reg_offset); 405 amdgpu_ring_write(ring, 406 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 407 } 408 amdgpu_ring_write(ring, val); 409 } 410 411 static void jpeg_v1_0_decode_ring_nop(struct amdgpu_ring *ring, uint32_t count) 412 { 413 int i; 414 415 WARN_ON(ring->wptr % 2 || count % 2); 416 417 for (i = 0; i < count / 2; i++) { 418 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 419 amdgpu_ring_write(ring, 0); 420 } 421 } 422 423 static int jpeg_v1_0_set_interrupt_state(struct amdgpu_device *adev, 424 struct amdgpu_irq_src *source, 425 unsigned type, 426 enum amdgpu_interrupt_state state) 427 { 428 return 0; 429 } 430 431 static int jpeg_v1_0_process_interrupt(struct amdgpu_device *adev, 432 struct amdgpu_irq_src *source, 433 struct amdgpu_iv_entry *entry) 434 { 435 DRM_DEBUG("IH: JPEG decode TRAP\n"); 436 437 switch (entry->src_id) { 438 case 126: 439 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 440 break; 441 default: 442 DRM_ERROR("Unhandled interrupt: %d %d\n", 443 entry->src_id, entry->src_data[0]); 444 break; 445 } 446 447 return 0; 448 } 449 450 /** 451 * jpeg_v1_0_early_init - set function pointers 452 * 453 * @handle: amdgpu_device pointer 454 * 455 * Set ring and irq function pointers 456 */ 457 int jpeg_v1_0_early_init(void *handle) 458 { 459 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 460 461 adev->jpeg.num_jpeg_inst = 1; 462 463 jpeg_v1_0_set_dec_ring_funcs(adev); 464 jpeg_v1_0_set_irq_funcs(adev); 465 466 return 0; 467 } 468 469 /** 470 * jpeg_v1_0_sw_init - sw init for JPEG block 471 * 472 * @handle: amdgpu_device pointer 473 * 474 */ 475 int jpeg_v1_0_sw_init(void *handle) 476 { 477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 478 struct amdgpu_ring *ring; 479 int r; 480 481 /* JPEG TRAP */ 482 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq); 483 if (r) 484 return r; 485 486 ring = &adev->jpeg.inst->ring_dec; 487 snprintf(ring->name, sizeof(ring->name), "jpeg_dec"); 488 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0); 489 if (r) 490 return r; 491 492 adev->jpeg.internal.jpeg_pitch = adev->jpeg.inst->external.jpeg_pitch = 493 SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 494 495 return 0; 496 } 497 498 /** 499 * jpeg_v1_0_sw_fini - sw fini for JPEG block 500 * 501 * @handle: amdgpu_device pointer 502 * 503 * JPEG free up sw allocation 504 */ 505 void jpeg_v1_0_sw_fini(void *handle) 506 { 507 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 508 509 amdgpu_ring_fini(&adev->jpeg.inst[0].ring_dec); 510 } 511 512 /** 513 * jpeg_v1_0_start - start JPEG block 514 * 515 * @adev: amdgpu_device pointer 516 * 517 * Setup and start the JPEG block 518 */ 519 void jpeg_v1_0_start(struct amdgpu_device *adev, int mode) 520 { 521 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 522 523 if (mode == 0) { 524 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 525 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 526 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 527 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); 528 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); 529 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 530 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 531 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 532 } 533 534 /* initialize wptr */ 535 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 536 537 /* copy patch commands to the jpeg ring */ 538 jpeg_v1_0_decode_ring_set_patch_ring(ring, 539 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); 540 } 541 542 static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = { 543 .type = AMDGPU_RING_TYPE_VCN_JPEG, 544 .align_mask = 0xf, 545 .nop = PACKET0(0x81ff, 0), 546 .support_64bit_ptrs = false, 547 .no_user_fence = true, 548 .vmhub = AMDGPU_MMHUB_0, 549 .extra_dw = 64, 550 .get_rptr = jpeg_v1_0_decode_ring_get_rptr, 551 .get_wptr = jpeg_v1_0_decode_ring_get_wptr, 552 .set_wptr = jpeg_v1_0_decode_ring_set_wptr, 553 .emit_frame_size = 554 6 + 6 + /* hdp invalidate / flush */ 555 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 556 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 557 8 + /* jpeg_v1_0_decode_ring_emit_vm_flush */ 558 26 + 26 + /* jpeg_v1_0_decode_ring_emit_fence x2 vm fence */ 559 6, 560 .emit_ib_size = 22, /* jpeg_v1_0_decode_ring_emit_ib */ 561 .emit_ib = jpeg_v1_0_decode_ring_emit_ib, 562 .emit_fence = jpeg_v1_0_decode_ring_emit_fence, 563 .emit_vm_flush = jpeg_v1_0_decode_ring_emit_vm_flush, 564 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 565 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 566 .insert_nop = jpeg_v1_0_decode_ring_nop, 567 .insert_start = jpeg_v1_0_decode_ring_insert_start, 568 .insert_end = jpeg_v1_0_decode_ring_insert_end, 569 .pad_ib = amdgpu_ring_generic_pad_ib, 570 .begin_use = vcn_v1_0_ring_begin_use, 571 .end_use = amdgpu_vcn_ring_end_use, 572 .emit_wreg = jpeg_v1_0_decode_ring_emit_wreg, 573 .emit_reg_wait = jpeg_v1_0_decode_ring_emit_reg_wait, 574 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 575 }; 576 577 static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 578 { 579 adev->jpeg.inst->ring_dec.funcs = &jpeg_v1_0_decode_ring_vm_funcs; 580 DRM_INFO("JPEG decode is enabled in VM mode\n"); 581 } 582 583 static const struct amdgpu_irq_src_funcs jpeg_v1_0_irq_funcs = { 584 .set = jpeg_v1_0_set_interrupt_state, 585 .process = jpeg_v1_0_process_interrupt, 586 }; 587 588 static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev) 589 { 590 adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs; 591 } 592
Indexes created Sat Sep 20 22:09:52 GMT 2025