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Searched refs:mmUVD_LMI_STATUS (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`52 #define mmUVD_LMI_STATUS 0x3D67`
uvd_4_2_d.h	`52 #define mmUVD_LMI_STATUS 0x3d67`
uvd_5_0_d.h	`58 #define mmUVD_LMI_STATUS 0x3d67`
uvd_6_0_d.h	`74 #define mmUVD_LMI_STATUS 0x3d67`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c	`406 status = RREG32(mmUVD_LMI_STATUS); 420 status = RREG32(mmUVD_LMI_STATUS);`
amdgpu_vcn_v1_0.c	`1131 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1140 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);`
amdgpu_vcn_v2_0.c	`1092 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); 1103 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);`
amdgpu_vcn_v2_5.c	`1323 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r); 1334 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`340 #define mmUVD_LMI_STATUS 0x0567`
vcn_2_0_0_offset.h	`566 #define mmUVD_LMI_STATUS 0x0227`
vcn_2_5_offset.h	`963 #define mmUVD_LMI_STATUS 0x04a9`

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