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Searched refs:mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_7_0_offset.h	`72 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x03ec`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`162 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x03ec`
vcn_2_0_0_offset.h	`826 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x05ac`
vcn_2_5_offset.h	`871 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c	`419 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 484 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 493 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 1196 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),`
amdgpu_vcn_v2_0.c	`335 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 401 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 410 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);`
amdgpu_uvd_v7_0.c	`689 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 832 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),`
amdgpu_vcn_v1_0.c	`323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 393 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,`

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