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Searched refs:mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_7_0_offset.h	`78 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x03f1`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`168 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x03f1`
vcn_2_0_0_offset.h	`836 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x05b1`
vcn_2_5_offset.h	`881 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c	`429 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 507 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1215 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),`
amdgpu_uvd_v7_0.c	`698 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 841 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),`
amdgpu_vcn_v1_0.c	`333 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 406 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,`
amdgpu_vcn_v2_0.c	`345 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 424 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),`

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