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Searched refs:mmUVD_MIF_RECON1_ADDR_CONFIG (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_d.h	`113 #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5`
uvd_6_0_d.h	`129 #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`97 #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5`
vcn_2_5_offset.h	`845 #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x03e1`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`350 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 426 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,`

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