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    Searched refs:mmUVD_MPC_CNTL (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 55 #define mmUVD_MPC_CNTL 0x3D77
uvd_4_2_d.h 55 #define mmUVD_MPC_CNTL 0x3d77
uvd_5_0_d.h 61 #define mmUVD_MPC_CNTL 0x3d77
uvd_6_0_d.h 77 #define mmUVD_MPC_CNTL 0x3d77
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 295 tmp = RREG32(mmUVD_MPC_CNTL);
296 WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
amdgpu_vcn_v1_0.c 821 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
824 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
1006 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
amdgpu_vcn_v2_0.c 793 UVD, 0, mmUVD_MPC_CNTL),
914 /* setup mmUVD_MPC_CNTL */
915 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
918 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
amdgpu_vcn_v2_5.c 801 UVD, 0, mmUVD_MPC_CNTL),
941 /* setup mmUVD_MPC_CNTL */
942 tmp = RREG32_SOC15(UVD, i, mmUVD_MPC_CNTL);
945 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 346 #define mmUVD_MPC_CNTL 0x0577
vcn_2_0_0_offset.h 594 #define mmUVD_MPC_CNTL 0x0237
vcn_2_5_offset.h 759 #define mmUVD_MPC_CNTL 0x02cc

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