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Searched refs:mmUVD_PGFSM_STATUS (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_jpeg_v2_0.c	`240 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 270 SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,`
amdgpu_vcn_v1_0.c	`709 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); 723 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); 774 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);`
amdgpu_vcn_v2_0.c	`681 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 695 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret); 746 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`32 #define mmUVD_PGFSM_STATUS 0x00c1`
vcn_2_0_0_offset.h	`384 #define mmUVD_PGFSM_STATUS 0x0001`
vcn_2_5_offset.h	`399 #define mmUVD_PGFSM_STATUS 0x0001`

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