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Searched refs:mmUVD_RB_BASE_HI2 (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_d.h	`42 #define mmUVD_RB_BASE_HI2 0x3c22`
uvd_7_0_offset.h	`88 #define mmUVD_RB_BASE_HI2 0x0422`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`210 #define mmUVD_RB_BASE_HI2 0x0422`
vcn_2_0_0_offset.h	`922 #define mmUVD_RB_BASE_HI2 0x05e2`
vcn_2_5_offset.h	`565 #define mmUVD_RB_BASE_HI2 0x00b0`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`951 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1252 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));`
amdgpu_vcn_v2_0.c	`1036 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1178 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));`
amdgpu_vcn_v2_5.c	`1067 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1408 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));`
amdgpu_uvd_v6_0.c	`857 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));`
amdgpu_uvd_v7_0.c	`1111 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));`

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