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    Searched refs:mmUVD_RB_BASE_LO (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_d.h 46 #define mmUVD_RB_BASE_LO 0x3c26
uvd_7_0_offset.h 96 #define mmUVD_RB_BASE_LO 0x0426
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 218 #define mmUVD_RB_BASE_LO 0x0426
vcn_2_0_0_offset.h 930 #define mmUVD_RB_BASE_LO 0x05e6
vcn_2_5_offset.h 553 #define mmUVD_RB_BASE_LO 0x00aa
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c 1059 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1229 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1400 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
amdgpu_uvd_v7_0.c 908 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
1103 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
amdgpu_vcn_v1_0.c 943 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
amdgpu_vcn_v2_0.c 1028 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1170 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
amdgpu_uvd_v6_0.c 849 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);

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