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Searched refs:mmUVD_RB_BASE_LO2 (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_d.h	`41 #define mmUVD_RB_BASE_LO2 0x3c21`
uvd_7_0_offset.h	`86 #define mmUVD_RB_BASE_LO2 0x0421`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`208 #define mmUVD_RB_BASE_LO2 0x0421`
vcn_2_0_0_offset.h	`920 #define mmUVD_RB_BASE_LO2 0x05e1`
vcn_2_5_offset.h	`563 #define mmUVD_RB_BASE_LO2 0x00af`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`950 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1251 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);`
amdgpu_vcn_v2_0.c	`1035 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1177 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);`
amdgpu_vcn_v2_5.c	`1066 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1407 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);`
amdgpu_uvd_v6_0.c	`856 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);`
amdgpu_uvd_v7_0.c	`1110 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);`

Completed in 29 milliseconds