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    Searched refs:mmUVD_RB_RPTR (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_d.h 49 #define mmUVD_RB_RPTR 0x3c29
uvd_7_0_offset.h 102 #define mmUVD_RB_RPTR 0x0429
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 224 #define mmUVD_RB_RPTR 0x0429
vcn_2_0_0_offset.h 936 #define mmUVD_RB_RPTR 0x05e9
vcn_2_5_offset.h 559 #define mmUVD_RB_RPTR 0x00ad
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c 941 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1174 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1586 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
amdgpu_vcn_v2_0.c 1026 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1053 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1173 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1469 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
amdgpu_vcn_v2_5.c 1057 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1283 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1403 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1526 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
amdgpu_uvd_v6_0.c 101 return RREG32(mmUVD_RB_RPTR);
847 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
amdgpu_uvd_v7_0.c 97 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
1101 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

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