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Searched refs:mmUVD_RB_SIZE (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_d.h	`48 #define mmUVD_RB_SIZE 0x3c28`
uvd_7_0_offset.h	`100 #define mmUVD_RB_SIZE 0x0428`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`222 #define mmUVD_RB_SIZE 0x0428`
vcn_2_0_0_offset.h	`934 #define mmUVD_RB_SIZE 0x05e8`
vcn_2_5_offset.h	`557 #define mmUVD_RB_SIZE 0x00ac`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c	`1061 WREG32_SOC15(UVD, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1235 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), 1402 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);`
amdgpu_uvd_v7_0.c	`910 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); 1105 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);`
amdgpu_vcn_v1_0.c	`945 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);`
amdgpu_vcn_v2_0.c	`1030 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1172 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);`
amdgpu_uvd_v6_0.c	`851 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);`

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