OpenGrok
Home
Sort by:
relevance
|
last modified time
|
path
Full Search
in project(s):
src
Definition
Symbol
File Path
History
|
|
Help
Searched
refs:mmUVD_RB_WPTR
(Results
1 - 10
of
10
) sorted by relevancy
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_d.h
50
#define
mmUVD_RB_WPTR
0x3c2a
uvd_7_0_offset.h
104
#define
mmUVD_RB_WPTR
0x042a
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h
226
#define
mmUVD_RB_WPTR
0x042a
vcn_2_0_0_offset.h
938
#define
mmUVD_RB_WPTR
0x05ea
vcn_2_5_offset.h
561
#define
mmUVD_RB_WPTR
0x00ae
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c
942
WREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
1173
tmp = RREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
);
1248
WREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
1603
return RREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
);
1620
WREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
,
amdgpu_vcn_v2_0.c
1027
WREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
1052
tmp = RREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
);
1174
WREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
1489
return RREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
);
1514
WREG32_SOC15(UVD, 0,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
amdgpu_vcn_v2_5.c
1058
WREG32_SOC15(UVD, i,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
1282
tmp = RREG32_SOC15(UVD, inst_idx,
mmUVD_RB_WPTR
);
1404
WREG32_SOC15(UVD, inst_idx,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
1546
return RREG32_SOC15(UVD, ring->me,
mmUVD_RB_WPTR
);
1571
WREG32_SOC15(UVD, ring->me,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
amdgpu_uvd_v6_0.c
131
return RREG32(
mmUVD_RB_WPTR
);
162
WREG32(
mmUVD_RB_WPTR
,
848
WREG32(
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
amdgpu_uvd_v7_0.c
131
return RREG32_SOC15(UVD, ring->me,
mmUVD_RB_WPTR
);
169
WREG32_SOC15(UVD, ring->me,
mmUVD_RB_WPTR
,
1102
WREG32_SOC15(UVD, k,
mmUVD_RB_WPTR
, lower_32_bits(ring->wptr));
Completed in 47 milliseconds
Indexes created Mon Oct 20 11:09:49 GMT 2025