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Searched refs:mmUVD_SEMA_CNTL (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`80 #define mmUVD_SEMA_CNTL 0x3D00`
uvd_4_2_d.h	`40 #define mmUVD_SEMA_CNTL 0x3d00`
uvd_5_0_d.h	`46 #define mmUVD_SEMA_CNTL 0x3d00`
uvd_6_0_d.h	`57 #define mmUVD_SEMA_CNTL 0x3d00`
uvd_7_0_offset.h	`124 #define mmUVD_SEMA_CNTL 0x0500`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`250 #define mmUVD_SEMA_CNTL 0x0500`
vcn_2_0_0_offset.h	`478 #define mmUVD_SEMA_CNTL 0x01c0`
vcn_2_5_offset.h	`817 #define mmUVD_SEMA_CNTL 0x02ef`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c	`196 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));`
amdgpu_uvd_v5_0.c	`193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));`
amdgpu_uvd_v6_0.c	`508 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));`
amdgpu_uvd_v7_0.c	`578 mmUVD_SEMA_CNTL), 0));`

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