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Searched refs:mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`83 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3DB2`
uvd_4_2_d.h	`81 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2`
uvd_5_0_d.h	`87 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2`
uvd_6_0_d.h	`103 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2`
uvd_7_0_offset.h	`214 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x05b2`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`402 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x05b2`
vcn_2_0_0_offset.h	`706 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x0272`
vcn_2_5_offset.h	`821 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c	`180 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);`
amdgpu_uvd_v5_0.c	`177 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);`
amdgpu_uvd_v6_0.c	`492 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);`
amdgpu_uvd_v7_0.c	`558 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);`

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