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    Searched refs:mmUVD_SYS_INT_EN (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 334 #define mmUVD_SYS_INT_EN 0x0541
vcn_2_0_0_offset.h 542 #define mmUVD_SYS_INT_EN 0x0201
vcn_2_5_offset.h 537 #define mmUVD_SYS_INT_EN 0x00a2
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c 898 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
1061 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,

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