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    Searched refs:mmVML2PF0_VM_L2_CNTL2 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mmhub_v9_4.c 236 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
242 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
mmhub_9_4_1_offset.h 3902 #define mmVML2PF0_VM_L2_CNTL2 0x09c1

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