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    Searched refs:mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mmhub_v9_4.c 191 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
209 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
416 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
424 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
mmhub_9_4_1_offset.h 4432 #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL 0x0b07

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