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    Searched refs:mmVM_CONTEXT0_CNTL (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c 188 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
193 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
312 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
389 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
amdgpu_gmc_v6_0.c 536 WREG32(mmVM_CONTEXT0_CNTL,
614 WREG32(mmVM_CONTEXT0_CNTL, 0);
1077 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1079 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1085 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1087 WREG32(mmVM_CONTEXT0_CNTL, tmp);
amdgpu_gmc_v7_0.c 673 tmp = RREG32(mmVM_CONTEXT0_CNTL);
677 WREG32(mmVM_CONTEXT0_CNTL, tmp);
757 WREG32(mmVM_CONTEXT0_CNTL, 0);
1262 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1264 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1272 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1274 WREG32(mmVM_CONTEXT0_CNTL, tmp);
amdgpu_mmhub_v1_0.c 207 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
212 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
346 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
431 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
amdgpu_gmc_v8_0.c 910 tmp = RREG32(mmVM_CONTEXT0_CNTL);
914 WREG32(mmVM_CONTEXT0_CNTL, tmp);
995 WREG32(mmVM_CONTEXT0_CNTL, 0);
1428 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1430 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1438 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1440 WREG32(mmVM_CONTEXT0_CNTL, tmp);
amdgpu_si.c 92 mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_7_0_d.h 547 #define mmVM_CONTEXT0_CNTL 0x504
gmc_8_2_d.h 605 #define mmVM_CONTEXT0_CNTL 0x504
gmc_6_0_d.h 1219 #define mmVM_CONTEXT0_CNTL 0x0504
gmc_7_1_d.h 580 #define mmVM_CONTEXT0_CNTL 0x504
gmc_8_1_d.h 603 #define mmVM_CONTEXT0_CNTL 0x504
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
mmhub_1_0_offset.h 1326 #define mmVM_CONTEXT0_CNTL 0x06c0
mmhub_9_1_offset.h 1358 #define mmVM_CONTEXT0_CNTL 0x06c0
mmhub_9_3_0_offset.h 1342 #define mmVM_CONTEXT0_CNTL 0x06c0
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 1229 #define mmVM_CONTEXT0_CNTL 0x0880
gc_9_1_offset.h 1248 #define mmVM_CONTEXT0_CNTL 0x0880
gc_9_2_1_offset.h 1186 #define mmVM_CONTEXT0_CNTL 0x0880

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