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    Searched refs:mmVM_CONTEXT1_CNTL (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gmc_v6_0.c 417 tmp = RREG32(mmVM_CONTEXT1_CNTL);
430 WREG32(mmVM_CONTEXT1_CNTL, tmp);
566 WREG32(mmVM_CONTEXT1_CNTL,
615 WREG32(mmVM_CONTEXT1_CNTL, 0);
1080 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1082 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1088 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1090 WREG32(mmVM_CONTEXT1_CNTL, tmp);
amdgpu_gmc_v7_0.c 538 tmp = RREG32(mmVM_CONTEXT1_CNTL);
551 WREG32(mmVM_CONTEXT1_CNTL, tmp);
703 tmp = RREG32(mmVM_CONTEXT1_CNTL);
708 WREG32(mmVM_CONTEXT1_CNTL, tmp);
758 WREG32(mmVM_CONTEXT1_CNTL, 0);
1266 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1268 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1276 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1278 WREG32(mmVM_CONTEXT1_CNTL, tmp);
amdgpu_gmc_v8_0.c 757 tmp = RREG32(mmVM_CONTEXT1_CNTL);
772 WREG32(mmVM_CONTEXT1_CNTL, tmp);
940 tmp = RREG32(mmVM_CONTEXT1_CNTL);
952 WREG32(mmVM_CONTEXT1_CNTL, tmp);
996 WREG32(mmVM_CONTEXT1_CNTL, 0);
1432 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1434 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1442 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1444 WREG32(mmVM_CONTEXT1_CNTL, tmp);
amdgpu_gfxhub_v1_0.c 227 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
253 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
amdgpu_mmhub_v1_0.c 250 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
276 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_7_0_d.h 548 #define mmVM_CONTEXT1_CNTL 0x505
gmc_8_2_d.h 606 #define mmVM_CONTEXT1_CNTL 0x505
gmc_6_0_d.h 1233 #define mmVM_CONTEXT1_CNTL 0x0505
gmc_7_1_d.h 581 #define mmVM_CONTEXT1_CNTL 0x505
gmc_8_1_d.h 604 #define mmVM_CONTEXT1_CNTL 0x505
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
mmhub_1_0_offset.h 1328 #define mmVM_CONTEXT1_CNTL 0x06c1
mmhub_9_1_offset.h 1360 #define mmVM_CONTEXT1_CNTL 0x06c1
mmhub_9_3_0_offset.h 1344 #define mmVM_CONTEXT1_CNTL 0x06c1
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 1231 #define mmVM_CONTEXT1_CNTL 0x0881
gc_9_1_offset.h 1250 #define mmVM_CONTEXT1_CNTL 0x0881
gc_9_2_1_offset.h 1188 #define mmVM_CONTEXT1_CNTL 0x0881

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