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    Searched refs:mmVM_L2_CNTL3 (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c 176 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
325 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
amdgpu_gmc_v6_0.c 525 WREG32(mmVM_L2_CNTL3,
627 WREG32(mmVM_L2_CNTL3,
amdgpu_mmhub_v1_0.c 195 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
362 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
amdgpu_gmc_v7_0.c 661 tmp = RREG32(mmVM_L2_CNTL3);
665 WREG32(mmVM_L2_CNTL3, tmp);
amdgpu_gmc_v8_0.c 883 tmp = RREG32(mmVM_L2_CNTL3);
887 WREG32(mmVM_L2_CNTL3, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_7_0_d.h 545 #define mmVM_L2_CNTL3 0x502
gmc_8_2_d.h 603 #define mmVM_L2_CNTL3 0x502
gmc_6_0_d.h 1261 #define mmVM_L2_CNTL3 0x0502
gmc_7_1_d.h 578 #define mmVM_L2_CNTL3 0x502
gmc_8_1_d.h 601 #define mmVM_L2_CNTL3 0x502
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
mmhub_1_0_offset.h 1270 #define mmVM_L2_CNTL3 0x0682
mmhub_9_1_offset.h 1302 #define mmVM_L2_CNTL3 0x0682
mmhub_9_3_0_offset.h 1286 #define mmVM_L2_CNTL3 0x0682
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 1166 #define mmVM_L2_CNTL3 0x0842
gc_9_1_offset.h 1192 #define mmVM_L2_CNTL3 0x0842
gc_9_2_1_offset.h 1130 #define mmVM_L2_CNTL3 0x0842

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