/src/sys/external/bsd/drm2/dist/drm/sis/ |
sis_drv.h | 53 #define SIS_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) 54 #define SIS_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) 57 drm_local_map_t *mmio; member in struct:drm_sis_private
|
sis_mm.c | 259 if (dev_priv->mmio == NULL) { 260 dev_priv->mmio = sis_reg_init(dev); 261 if (dev_priv->mmio == NULL) { 319 dev_priv->mmio = NULL;
|
/src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
mmio_context.c | 203 struct engine_mmio *mmio; local in function:restore_context_mmio_for_inhibit 220 for (mmio = gvt->engine_mmio_list.mmio; 221 i915_mmio_reg_valid(mmio->reg); mmio++) { 222 if (mmio->ring_id != ring_id || 223 !mmio->in_context) 226 *cs++ = i915_mmio_reg_offset(mmio->reg); 227 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | 228 (mmio->mask << 16) 479 struct engine_mmio *mmio; local in function:switch_mmio 586 struct engine_mmio *mmio; local in function:intel_gvt_init_engine_mmio_context [all...] |
mmio.c | 1 /* $NetBSD: mmio.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */ 39 __KERNEL_RCSID(0, "$NetBSD: mmio.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $"); 45 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset 98 * intel_vgpu_emulate_mmio_read - emulate MMIO read 162 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n", 170 * intel_vgpu_emulate_mmio_write - emulate MMIO write 226 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, 235 * intel_vgpu_reset_mmio - reset virtual MMIO space 243 void *mmio = gvt->firmware.mmio; local in function:intel_vgpu_reset_mmio [all...] |
Makefile | 4 interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
|
gvt.h | 40 #include "mmio.h" 190 struct intel_vgpu_mmio mmio; member in struct:intel_vgpu 249 /* Special MMIO blocks. */ 288 void *mmio; member in struct:intel_gvt_firmware 317 struct intel_gvt_mmio mmio; member in struct:intel_gvt 337 struct engine_mmio *mmio; member in struct:intel_gvt::__anon1940818c0408 446 Explicitly seperate use for typed MMIO reg or real offset.*/ 448 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 450 (*(u32 *)(vgpu->mmio.vreg + (offset))) 452 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)) [all...] |
firmware.c | 116 /* Take a snapshot of hw mmio registers. */ 119 memcpy(gvt->firmware.mmio, p, info->mmio_size); 154 vfree(gvt->firmware.mmio); 184 VERIFY("mmio size", h->mmio_size, info->mmio_size); 244 firmware->mmio = mem; 270 memcpy(firmware->mmio, fw->data + h->mmio_offset,
|
/src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/ |
pci.h | 19 bool detect, bool mmio, u64 subdev_mask,
|
tegra.h | 57 bool detect, bool mmio, u64 subdev_mask,
|
/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
nouveau_nvkm_subdev_devinit_gt215.c | 111 u32 *mmio = gt215_devinit_mmio_part; local in function:gt215_devinit_mmio 128 while (mmio[0]) { 129 if (addr >= mmio[0] && addr <= mmio[1]) { 130 u32 part = (addr / mmio[2]) & 7; 137 mmio += 3; 148 .mmio = gt215_devinit_mmio,
|
priv.h | 14 u32 (*mmio)(struct nvkm_devinit *, u32); member in struct:nvkm_devinit_func
|
nouveau_nvkm_subdev_devinit_base.c | 37 if (init->func->mmio) 38 addr = init->func->mmio(init, addr);
|
/src/sys/external/bsd/drm/dist/shared-core/ |
sis_drv.h | 54 #define SIS_BASE (dev_priv->mmio) 59 drm_local_map_t *mmio; member in struct:drm_sis_private
|
radeon_irq.c | 68 if (!dev_priv->mmio) 106 if (!dev_priv->mmio) 298 if (!dev_priv->mmio) 333 if (!dev_priv->mmio) 357 if (!dev_priv->mmio)
|
r128_drv.h | 119 drm_local_map_t *mmio; member in struct:drm_r128_private 393 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 394 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 395 #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 396 #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
|
mga_drv.h | 111 * \name MMIO region parameters. 113 * \sa drm_mga_private_t::mmio 116 u32 mmio_base; /**< Bus address of base of MMIO. */ 117 u32 mmio_size; /**< Size of the MMIO region. */ 142 drm_local_map_t *mmio; member in struct:drm_mga_private 200 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) 217 #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) 218 #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) 219 #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 220 #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val) [all...] |
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
at91sam9xe.dtsi | 20 compatible = "mmio-sram";
|
at91sam9g20.dtsi | 23 compatible = "mmio-sram";
|
imx6qp.dtsi | 10 compatible = "mmio-sram"; 16 compatible = "mmio-sram";
|
/src/sys/external/bsd/drm2/dist/drm/via/ |
via_map.c | 59 dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset); 60 if (!dev_priv->mmio) { 61 DRM_ERROR("could not find mmio region!\n");
|
via_drv.h | 85 drm_local_map_t *mmio; member in struct:drm_via_private 139 /* VIA MMIO register access */ 142 return DRM_READ32(dev_priv->mmio, reg); 148 DRM_WRITE32(dev_priv->mmio, reg, val); 154 DRM_WRITE8(dev_priv->mmio, reg, val); 162 tmp = DRM_READ8(dev_priv->mmio, reg); 164 DRM_WRITE8(dev_priv->mmio, reg, tmp);
|
/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
nouveau_nvkm_engine_gr_gf110.c | 109 .mmio = gf110_gr_pack_mmio,
|
/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
priv.h | 61 bool detect, bool mmio, u64 subdev_mask,
|
nouveau_nvkm_engine_device_tegra.c | 294 bool detect, bool mmio, u64 subdev_mask, 372 cfg, dbg, detect, mmio, subdev_mask, 394 bool detect, bool mmio, u64 subdev_mask,
|
/src/sys/external/bsd/drm2/dist/drm/r128/ |
r128_drv.h | 131 drm_local_map_t *mmio; member in struct:drm_r128_private 409 #define R128_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) 410 #define R128_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) 411 #define R128_READ8(reg) readb(((void __iomem *)dev_priv->mmio->handle) + (reg)) 412 #define R128_WRITE8(reg, val) writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
|