/src/sys/external/bsd/drm2/dist/drm/radeon/ |
radeon_evergreen_cs.c | 1212 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg 1215 &bankw, &bankh, &mtaspect, 1221 DB_MACRO_TILE_ASPECT(mtaspect); 1476 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg 1479 &bankw, &bankh, &mtaspect, 1485 CB_MACRO_TILE_ASPECT(mtaspect); 1504 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg 1507 &bankw, &bankh, &mtaspect, 1513 CB_MACRO_TILE_ASPECT(mtaspect); 2393 unsigned bankw, bankh, mtaspect, tile_split local in function:evergreen_packet3_check [all...] |
radeon_object.c | 697 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; local in function:radeon_bo_set_tiling_flags 701 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 724 switch (mtaspect) {
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radeon_atombios_crtc.c | 1161 unsigned bankw, bankh, mtaspect, tile_split; local in function:dce4_crtc_do_set_base 1283 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1351 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
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radeon_evergreen.c | 1120 unsigned *bankh, unsigned *mtaspect, 1125 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 1141 switch (*mtaspect) { 1143 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break; 1144 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break; 1145 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break; 1146 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
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radeon.h | 369 unsigned *bankh, unsigned *mtaspect,
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/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_dce_v10_0.c | 1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v10_0_crtc_do_set_base 1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2010 mtaspect);
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amdgpu_dce_v11_0.c | 2036 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v11_0_crtc_do_set_base 2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2052 mtaspect);
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amdgpu_dce_v6_0.c | 1943 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v6_0_crtc_do_set_base 1947 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1956 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
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amdgpu_dce_v8_0.c | 1915 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v8_0_crtc_do_set_base 1919 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1928 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
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/src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
amdgpu_dm.c | 3263 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; local in function:fill_plane_buffer_attributes 3267 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 3278 tiling_info->gfx8.tile_aspect = mtaspect;
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