| /src/sys/arch/vax/vax/ |
| ka53.c | 157 mtpr(0, PR_ICSR);
158 mtpr(0, PR_PCCTL);
159 mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
164 mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
165 mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
166 mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
167 mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
175 mtpr(0, start);
177 mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
185 mtpr(0, start)
[all...] |
| ka49.c | 142 mtpr(0, PR_ICSR);
143 mtpr(0, PR_PCCTL);
144 mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
149 mtpr(mfpr(PR_CCTL) | 0x10, PR_CCTL); /* Set cache size */
150 mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
151 mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
152 mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
159 mtpr(0, start);
161 mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
169 mtpr(0, start)
[all...] |
| ka680.c | 153 mtpr(0, PR_ICSR);
154 mtpr(0, PR_PCCTL);
155 mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
160 mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
161 mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
162 mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
163 mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
213 mtpr(0, start);
215 mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
222 mtpr(0, start)
[all...] |
| ka670.c | 118 mtpr(0x00, PR_MCESR); /* Acknowledge the machine check */
177 mtpr(KA670_PCS_REFRESH, PR_PCSTS); /* disable primary cache */
179 mtpr(val, PR_PCSTS); /* clear error flags */
180 mtpr(8, PR_BCCTL); /* disable backup cache */
181 mtpr(0, PR_BCFBTS); /* flush backup cache tag store */
182 mtpr(0, PR_BCFPTS); /* flush primary cache tag store */
183 mtpr(0x0e, PR_BCCTL); /* enable backup cache */
184 mtpr(KA670_PCS_FLUSH | KA670_PCS_REFRESH, PR_PCSTS); /* flush primary cache */
185 mtpr(KA670_PCS_ENABLE | KA670_PCS_REFRESH, PR_PCSTS); /* flush primary cache */
|
| ka46.c | 88 mtpr(2, PR_ACCS); /* Enable floating points */
104 mtpr(PCSTS_FLUSH, PR_PCSTS); /* primary */
114 mtpr(i << 3, PR_PCIDX);
115 mtpr(PCTAG_PARITY, PR_PCTAG);
125 mtpr(PCSTS_ENABLE, PR_PCSTS);
|
| ka43.c | 134 mtpr(0x00, PR_MCESR); /* Acknowledge the machine check */
233 mtpr(KA43_PCS_REFRESH, PR_PCSTS); /* disable primary cache */
235 mtpr(val, PR_PCSTS); /* clear error flags */
255 mtpr(i*8, PR_PCIDX); /* write index of tag */
256 mtpr(val, PR_PCTAG); /* write value into tag */
259 mtpr(val, PR_PCSTS); /* flush primary cache */
286 mtpr(val, PR_PCSTS); /* flush primary cache */
299 mtpr(val, PR_PCSTS); /* enable primary cache */
|
| ka48.c | 84 mtpr(2, PR_ACCS); /* Enable floating points */
100 mtpr(0, PR_CADR); /* disable */
102 mtpr(2, PR_CADR); /* flush */
109 mtpr(4, PR_CADR); /* enable cache */
|
| ka660.c | 100 mtpr(0, KA660_CCR); /* Disable cache */
101 mtpr(CCR_DIA, KA660_CCR); /* Switch to diag mode */
121 mtpr(CCR_DIA|CCR_FLU, KA660_CCR); /* Flush tags */
122 mtpr(CCR_ENA, KA660_CCR); /* Enable cache */
|
| ctu.c | 150 mtpr(0101, PR_CSTS); /* Enable transmit interrupt + send break */
152 mtpr(0, PR_CSTD); WAIT;
153 mtpr(0, PR_CSTD); WAIT;
154 mtpr(RSP_TYP_INIT, PR_CSTD); WAIT;
155 mtpr(RSP_TYP_INIT, PR_CSTD); WAIT;
173 mtpr(0100, PR_CSRS); /* Enable receive interrupt */
174 mtpr(0101, PR_CSTS); /* Enable transmit interrupt + send break */
196 mtpr(0, PR_CSRS);
197 mtpr(0, PR_CSTS);
379 mtpr(RSP_TYP_DATA, PR_CSTD)
[all...] |
| ka860.c | 107 * register must immediately follow the mtpr instruction that setup
149 * are defined correctly above and in mtpr.h.
151 __asm("mtpr $0x27,$0x4e; mfpr $0x4f,%0" : "=g" (mdecc));
154 __asm("mtpr $0x2a,$0x4e; mfpr $0x4f,%0" : "=g" (mear));
155 __asm("mtpr $0x25,$0x4e; mfpr $0x4f,%0" : "=g" (mstat1));
156 __asm("mtpr $0x26,$0x4e; mfpr $0x4f,%0" : "=g" (mstat2));
170 mtpr(0, PR_EHSR);
171 mtpr(mfpr(PR_MERG) | M8600_ICRD, PR_MERG);
263 mtpr(0, PR_EHSR);
292 mtpr(3, PR_CSWP)
[all...] |
| gencons.c | 212 mtpr(ch, pr_txdb[minor(tp->t_dev)]);
276 if ((vax_cputype < VAX_TYP_UV2) || /* All older has MTPR console */
297 mtpr(GC_RIE, pr_rxcs[0]); /* Turn on interrupts */
298 mtpr(GC_TIE, pr_txcs[0]);
312 mtpr(0, PR_RXCS);
313 mtpr(0, PR_TXCS);
314 mtpr(0, PR_TBIA); /* ??? */
347 mtpr(ch, PR_TXDB); /* xmit character */
370 mtpr(0, PR_RXCS);
371 mtpr(0, PR_TXCS)
[all...] |
| crl.c | 199 mtpr(bp->b_blkno<<8 | STXCS_IE | CRL_F_READ, PR_STXCS);
202 mtpr(bp->b_blkno<<8 | STXCS_IE | CRL_F_WRITE, PR_STXCS);
248 mtpr(*crltab.crl_xaddr++, PR_STXDB);
249 mtpr(bp->b_blkno<<8 | STXCS_IE | CRL_F_WRITE, PR_STXCS);
254 mtpr(bp->b_blkno<<8 | STXCS_IE | CRL_F_READ, PR_STXCS);
260 mtpr(STXCS_IE | CRL_F_RETSTS, PR_STXCS);
267 mtpr(STXCS_IE | CRL_S_RETSTS, PR_STXCS);
281 mtpr(STXCS_IE | CRL_F_ABORT, PR_STXCS);
|
| ka6400.c | 146 mtpr(0, PR_VPSR); /* Can't use vector processor */
289 mtpr(KA670_PCS_REFRESH, PR_PCSTS); /* disable primary cache */
290 mtpr(mfpr(PR_PCSTS), PR_PCSTS); /* clear error flags */
291 mtpr(8, PR_BCCTL); /* disable backup cache */
292 mtpr(0, PR_BCFBTS); /* flush backup cache tag store */
293 mtpr(0, PR_BCFPTS); /* flush primary cache tag store */
294 mtpr(0x0e, PR_BCCTL); /* enable backup cache */
295 mtpr(KA670_PCS_FLUSH | KA670_PCS_REFRESH, PR_PCSTS); /* flush primary cache */
296 mtpr(KA670_PCS_ENABLE | KA670_PCS_REFRESH, PR_PCSTS); /* flush primary cache */
383 * It seems like mtpr to TXCD sets the V flag if it fails
[all...] |
| ka780.c | 139 mtpr(0, PR_SBIER);
141 ((mcr)->mc_reg[2] = (M780_HIER|M780_ERLOG)); mtpr(3<<14, PR_SBIER);
150 mtpr(0, PR_SBIER);
152 ((mcr)->mc_reg[2] = (M780_HIER|M780_ERLOG)); mtpr(3<<14, PR_SBIER);
161 mtpr(0, PR_SBIER);
163 ((mcr)->mc_reg[3] = (M780_HIER|M780_ERLOG)); mtpr(3<<14, PR_SBIER);
340 mtpr(sbifs &~ 0x2000000, PR_SBIFS);
341 mtpr(mfpr(PR_SBIER) | 0x70c0, PR_SBIER);
357 mtpr(0x200000, PR_SBIMT);
371 mtpr(0x8000, PR_ACCS)
[all...] |
| ka730.c | 177 mtpr(0xf, PR_MCESR);
190 mtpr(GC_CWFL|GC_CONS, PR_TXDB);
193 mtpr(GC_CCFL|GC_CONS, PR_TXDB);
|
| scb.c | 84 mtpr(avail_start, PR_SCBB);
110 mtpr(ipl + 1, PR_IPL);
139 mtpr(0, PR_IPL);
|
| ka750.c | 106 mtpr(1, PR_TODR);
121 mtpr(0x8000, PR_ACCS);
272 mtpr(0, PR_TBIA);
273 mtpr(0xf, PR_MCESR);
290 mtpr(GC_CWFL|GC_CONS, PR_TXDB);
293 mtpr(GC_CCFL|GC_CONS, PR_TXDB);
|
| cfl.c | 233 mtpr(bp->b_flags & B_READ ? FLOP_READSECT : FLOP_WRITSECT, PR_TXDB);
249 mtpr(bp->b_flags & B_READ ? FLOP_READSECT : FLOP_WRITSECT,
255 mtpr(FLOP_DATA | (int)bp->b_blkno % (CFL_SECTORS + 1), PR_TXDB);
260 mtpr(FLOP_DATA | (int)bp->b_blkno / CFL_SECTORS, PR_TXDB);
265 mtpr(FLOP_DATA | *cfltab.cfl_xaddr++, PR_TXDB);
|
| findcpu.c | 37 #include <machine/mtpr.h>
|
| lock_stubs.S | 105 mtpr %r3, $PR_IPL /* yes, raise IPL */
139 mtpr %r2, $PR_IPL /* no, restore saved ipl */
278 mtpr $IPL_HIGH, $PR_IPL /* block everything */
287 mtpr %r5, $PR_IPL /* restore IPL */
|
| /src/sys/arch/vax/include/ |
| intr.h | 36 #include <machine/mtpr.h>
80 mtpr(ipl, PR_IPL);
129 #define setsoftddb() ((void)mtpr(IPL_SOFTDDB, PR_SIRR))
137 mtpr(machdep, PR_SIRR);
|
| cpu.h | 49 #include <machine/mtpr.h>
164 mtpr(AST_OK,PR_ASTLVL); \
175 mtpr(1, PR_IPL);
176 mtpr(ipl, PR_IPL);
207 mtpr(AST_OK,PR_ASTLVL); \
221 mtpr(AST_OK,PR_ASTLVL); \
|
| /src/sys/arch/vax/boot/boot/ |
| autoconf.c | 36 #include "../include/mtpr.h"
161 mtpr(i, PR_SCBB);
179 mtpr(-10000, PR_NICR); /* Load in count register */
180 mtpr(0x800000d1, PR_ICCS); /* Start clock and enable interrupt */
182 mtpr(20, PR_IPL);
190 mtpr(IPL_HIGH, PR_IPL);
192 mtpr(0xc1, PR_ICCS);
200 mtpr(20, PR_IPL);
|
| ctu.c | 36 #include <machine/mtpr.h>
68 mtpr(RSP_TYP_INIT, PR_CSTD);
152 mtpr(c, PR_CSTD);
|
| /src/sys/arch/vax/boot/common/ |
| srt0.S | 68 mtpr $0x1f,$0x12 # Block all interrupts
69 mtpr $0,$0x18 # stop real time interrupt clock
|
