1 /* $NetBSD: ka43.c,v 1.36 2017/05/22 16:46:15 ragge Exp $ */ 2 /* 3 * Copyright (c) 1996 Ludd, University of Lule}, Sweden. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Ludd by Bertram Barth. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ka43.c,v 1.36 2017/05/22 16:46:15 ragge Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kernel.h> 37 38 #include <machine/sid.h> 39 #include <machine/nexus.h> 40 #include <machine/vsbus.h> 41 #include <machine/ka43.h> 42 #include <machine/clock.h> 43 44 static void ka43_conf(void); 45 static void ka43_steal_pages(void); 46 47 static int ka43_mchk(void *); 48 static void ka43_memerr(void); 49 #if 0 50 static void ka43_clear_errors(void); 51 #endif 52 static int ka43_cache_init(void); /* "int mapen" as argument? */ 53 static int ka43_cache_reset(void); 54 static int ka43_cache_enable(void); 55 static int ka43_cache_disable(void); 56 static int ka43_cache_invalidate(void); 57 static void ka43_halt(void); 58 static void ka43_reboot(int); 59 static void ka43_clrf(void); 60 61 static const char * const ka43_devs[] = { "cpu", "vsbus", NULL }; 62 63 const struct cpu_dep ka43_calls = { 64 .cpu_steal_pages = ka43_steal_pages, 65 .cpu_mchk = ka43_mchk, 66 .cpu_memerr = ka43_memerr, 67 .cpu_conf = ka43_conf, 68 .cpu_gettime = chip_gettime, 69 .cpu_settime = chip_settime, 70 .cpu_vups = 7, /* 7.6 VUP */ 71 .cpu_scbsz = 2, /* SCB pages */ 72 .cpu_halt = ka43_halt, 73 .cpu_reboot = ka43_reboot, 74 .cpu_clrf = ka43_clrf, 75 .cpu_devs = ka43_devs, 76 .cpu_flags = CPU_RAISEIPL, 77 }; 78 79 /* 80 * ka43_steal_pages() is called with MMU disabled, after that call MMU gets 81 * enabled. Thus we initialize these four pointers with physical addresses, 82 * but before leving ka43_steal_pages() we reset them to virtual addresses. 83 */ 84 static volatile struct ka43_cpu *ka43_cpu = (void*)KA43_CPU_BASE; 85 static volatile u_int *ka43_creg = (void*)KA43_CH2_CREG; 86 static volatile u_int *ka43_ctag = (void*)KA43_CT2_BASE; 87 88 #define KA43_MC_RESTART 0x00008000 /* Restart possible*/ 89 #define KA43_PSL_FPDONE 0x00010000 /* First Part Done */ 90 91 struct ka43_mcframe { /* Format of RigelMAX machine check frame: */ 92 int mc43_bcnt; /* byte count, always 24 (0x18) */ 93 int mc43_code; /* machine check type code and restart bit */ 94 int mc43_addr; /* most recent (faulting?) virtual address */ 95 int mc43_viba; /* contents of VIBA register */ 96 int mc43_sisr; /* ICCS bit 6 and SISR bits 15:0 */ 97 int mc43_istate; /* internal state */ 98 int mc43_sc; /* shift count register */ 99 int mc43_pc; /* trapped PC */ 100 int mc43_psl; /* trapped PSL */ 101 }; 102 103 static const char * const ka43_mctype[] = { 104 "no error (0)", /* Code 0: No error */ 105 "FPA: protocol error", /* Code 1-5: FPA errors */ 106 "FPA: illegal opcode", 107 "FPA: operand parity error", 108 "FPA: unknown status", 109 "FPA: result parity error", 110 "unused (6)", /* Code 6-7: Unused */ 111 "unused (7)", 112 "MMU error (TLB miss)", /* Code 8-9: MMU errors */ 113 "MMU error (TLB hit)", 114 "HW interrupt at unused IPL", /* Code 10: Interrupt error */ 115 "MOVCx impossible state", /* Code 11-13: Microcode errors */ 116 "undefined trap code (i-box)", 117 "undefined control store address", 118 "unused (14)", /* Code 14-15: Unused */ 119 "unused (15)", 120 "PC tag or data parity error", /* Code 16: Cache error */ 121 "data bus parity error", /* Code 17: Read error */ 122 "data bus error (NXM)", /* Code 18: Write error */ 123 "undefined data bus state", /* Code 19: Bus error */ 124 }; 125 #define MC43_MAX 19 126 127 static int ka43_error_count = 0; 128 129 int 130 ka43_mchk(void *addr) 131 { 132 struct ka43_mcframe *mcf = (void*)addr; 133 134 mtpr(0x00, PR_MCESR); /* Acknowledge the machine check */ 135 printf("machine check %d (0x%x)\n", mcf->mc43_code, mcf->mc43_code); 136 printf("reason: %s\n", ka43_mctype[mcf->mc43_code & 0xff]); 137 if (++ka43_error_count > 10) { 138 printf("error_count exceeded: %d\n", ka43_error_count); 139 return (-1); 140 } 141 142 /* 143 * If either the Restart flag is set or the First-Part-Done flag 144 * is set, and the TRAP2 (double error) bit is not set, then the 145 * error is recoverable. 146 */ 147 if (mfpr(PR_PCSTS) & KA43_PCS_TRAP2) { 148 printf("TRAP2 (double error) in ka43_mchk.\n"); 149 panic("unrecoverable state in ka43_mchk."); 150 return (-1); 151 } 152 if ((mcf->mc43_code & KA43_MC_RESTART) || 153 (mcf->mc43_psl & KA43_PSL_FPDONE)) { 154 printf("ka43_mchk: recovering from machine-check.\n"); 155 ka43_cache_reset(); /* reset caches */ 156 return (0); /* go on; */ 157 } 158 159 /* 160 * Unknown error state, panic/halt the machine! 161 */ 162 printf("ka43_mchk: unknown error state!\n"); 163 return (-1); 164 } 165 166 void 167 ka43_memerr(void) 168 { 169 char sbuf[256]; 170 171 /* 172 * Don\'t know what to do here. So just print some messages 173 * and try to go on... 174 */ 175 176 printf("memory error!\n"); 177 178 snprintb(sbuf, sizeof(sbuf), KA43_PCSTS_BITS, mfpr(PR_PCSTS)); 179 printf("primary cache status: %s\n", sbuf); 180 181 snprintb(sbuf, sizeof(sbuf), KA43_SESR_BITS, *ka43_creg); 182 printf("secondary cache status: %s\n", sbuf); 183 } 184 185 int 186 ka43_cache_init(void) 187 { 188 return (ka43_cache_reset()); 189 } 190 191 #if 0 192 void 193 ka43_clear_errors(void) 194 { 195 int val = *ka43_creg; 196 val |= KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR; 197 *ka43_creg = val; 198 } 199 #endif 200 201 int 202 ka43_cache_reset(void) 203 { 204 char sbuf[256]; 205 206 /* 207 * resetting primary and secondary caches is done in three steps: 208 * 1. disable both caches 209 * 2. manually clear secondary cache 210 * 3. enable both caches 211 */ 212 ka43_cache_disable(); 213 ka43_cache_invalidate(); 214 ka43_cache_enable(); 215 216 snprintb(sbuf, sizeof(sbuf), KA43_PCSTS_BITS, mfpr(PR_PCSTS)); 217 printf("primary cache status: %s\n", sbuf); 218 219 snprintb(sbuf, sizeof(sbuf), KA43_SESR_BITS, *ka43_creg); 220 printf("secondary cache status: %s\n", sbuf); 221 222 return (0); 223 } 224 225 int 226 ka43_cache_disable(void) 227 { 228 int val; 229 230 /* 231 * first disable primary cache and clear error flags 232 */ 233 mtpr(KA43_PCS_REFRESH, PR_PCSTS); /* disable primary cache */ 234 val = mfpr(PR_PCSTS); 235 mtpr(val, PR_PCSTS); /* clear error flags */ 236 237 /* 238 * now disable secondary cache and clear error flags 239 */ 240 val = *ka43_creg & ~KA43_SESR_CENB; /* BICL !!! */ 241 *ka43_creg = val; /* disable secondary cache */ 242 val = KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR; 243 *ka43_creg = val; /* clear error flags */ 244 245 return (0); 246 } 247 248 int 249 ka43_cache_invalidate(void) 250 { 251 int i, val; 252 253 val = KA43_PCTAG_PARITY; /* clear valid flag, set parity bit */ 254 for (i = 0; i < 256; i++) { /* 256 Quadword entries */ 255 mtpr(i*8, PR_PCIDX); /* write index of tag */ 256 mtpr(val, PR_PCTAG); /* write value into tag */ 257 } 258 val = KA43_PCS_FLUSH | KA43_PCS_REFRESH; 259 mtpr(val, PR_PCSTS); /* flush primary cache */ 260 261 /* 262 * Rigel\'s secondary cache doesn\'t implement a valid-flag. 263 * Thus we initialize all entries with out-of-range/dummy 264 * addresses which will never be referenced (ie. never hit). 265 * After enabling cache we also access 128K of memory starting 266 * at 0x00 so that secondary cache will be filled with these 267 * valid addresses... 268 */ 269 val = 0xff; 270 /* if (memory > 28 MB) val = 0x55; */ 271 for (i = 0; i < KA43_CT2_SIZE; i+= 4) { /* Quadword entries ?? */ 272 ka43_ctag[i/4] = val; /* reset upper and lower */ 273 } 274 275 return (0); 276 } 277 278 279 int 280 ka43_cache_enable(void) 281 { 282 volatile char *membase = (void*)0x80000000; /* physical 0x00 */ 283 int i, val; 284 285 val = KA43_PCS_FLUSH | KA43_PCS_REFRESH; 286 mtpr(val, PR_PCSTS); /* flush primary cache */ 287 288 /* 289 * now we enable secondary cache and access first 128K of memory 290 * so that secondary cache gets really initialized and holds 291 * valid addresses/data... 292 */ 293 *ka43_creg = KA43_SESR_CENB; /* enable secondary cache */ 294 for (i=0; i<128*1024; i++) { 295 val += membase[i]; /* some dummy operation... */ 296 } 297 298 val = KA43_PCS_ENABLE | KA43_PCS_REFRESH; 299 mtpr(val, PR_PCSTS); /* enable primary cache */ 300 301 return (0); 302 } 303 304 void 305 ka43_conf(void) 306 { 307 curcpu()->ci_cpustr = "Rigel, 2KB L1 cache, 128KB L2 cache"; 308 309 ka43_cpu = (void *)vax_map_physmem(VS_REGS, 1); 310 ka43_creg = (void *)vax_map_physmem(KA43_CH2_CREG, 1); 311 ka43_ctag = (void *)vax_map_physmem(KA43_CT2_BASE, 312 (KA43_CT2_SIZE/VAX_NBPG)); 313 314 /* 315 * ka43_conf() gets called with MMU enabled, now it's save to 316 * init/reset the caches. 317 */ 318 ka43_cache_init(); 319 320 clk_adrshift = 1; /* Addressed at long's... */ 321 clk_tweak = 2; /* ...and shift two */ 322 clk_page = (short *)vax_map_physmem(VS_CLOCK, 1); 323 } 324 325 326 /* 327 * The interface for communication with the LANCE ethernet controller 328 * is setup in the xxx_steal_pages() routine. We decrease highest 329 * available address by 64K and use this area as communication buffer. 330 */ 331 332 void 333 ka43_steal_pages(void) 334 { 335 int val; 336 337 338 /* 339 * if LANCE\'s io-buffer is above 16 MB, then the appropriate flag 340 * in the parity control register has to be set (it works as an 341 * additional address bit). In any case, don\'t enable CPEN and 342 * DPEN in the PARCTL register, somewhow they are internally managed 343 * by the RIGEL chip itself!?! 344 */ 345 val = ka43_cpu->parctl & 0x03; /* read the old value */ 346 ka43_cpu->parctl = val; /* and write new value */ 347 } 348 349 void 350 ka43_clrf(void) 351 { 352 volatile struct ka43_clock *clk = (volatile void *)clk_page; 353 354 /* 355 * Clear restart and boot in progress flags in the CPMBX. 356 * The cpmbx is split into two 4-bit fields. 357 * One for the current restart/boot in progress flags, and 358 * one for the permanent halt flag. 359 * The restart/boot in progress flag is also used as the action request 360 * for the CPU at a halt. /BQT 361 */ 362 clk->req = 0; 363 } 364 365 void 366 ka43_halt(void) 367 { 368 volatile struct ka43_clock *clk = (volatile void *)clk_page; 369 clk->req = 3; /* 3 is halt. */ 370 __asm("halt"); 371 } 372 373 void 374 ka43_reboot(int arg) 375 { 376 volatile struct ka43_clock *clk = (volatile void *)clk_page; 377 clk->req = 2; /* 2 is reboot. */ 378 __asm("halt"); 379 } 380
Indexes created Sun Sep 21 16:09:51 GMT 2025