| /src/external/gpl3/gdb/dist/sim/or1k/ |
| cpu.c | 42 or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 SET_H_PC (newval);
58 or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
60 SET_H_SPR (regno, newval);
74 or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
76 SET_H_GPR (regno, newval);
90 or1k32bf_h_fsr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
92 SET_H_FSR (regno, newval);
106 or1k32bf_h_fd32r_set (SIM_CPU *current_cpu, UINT regno, DF newval)
108 SET_H_FD32R (regno, newval);
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/or1k/ |
| cpu.c | 42 or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 SET_H_PC (newval);
58 or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
60 SET_H_SPR (regno, newval);
74 or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
76 SET_H_GPR (regno, newval);
90 or1k32bf_h_fsr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
92 SET_H_FSR (regno, newval);
106 or1k32bf_h_fd32r_set (SIM_CPU *current_cpu, UINT regno, DF newval)
108 SET_H_FD32R (regno, newval);
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/cris/ |
| cpuv32.c | 42 crisv32f_h_v32_v32_set (SIM_CPU *current_cpu, BI newval)
44 SET_H_V32_V32 (newval);
58 crisv32f_h_pc_set (SIM_CPU *current_cpu, USI newval)
60 SET_H_PC (newval);
74 crisv32f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
76 SET_H_GR (regno, newval);
90 crisv32f_h_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
92 CPU (h_gr_acr[regno]) = newval;
106 crisv32f_h_raw_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
108 SET_H_RAW_GR_ACR (regno, newval);
[all...] |
| cpuv10.c | 42 crisv10f_h_v32_non_v32_set (SIM_CPU *current_cpu, BI newval)
44 SET_H_V32_NON_V32 (newval);
58 crisv10f_h_pc_set (SIM_CPU *current_cpu, USI newval)
60 SET_H_PC (newval);
74 crisv10f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
76 SET_H_GR (regno, newval);
90 crisv10f_h_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
92 SET_H_GR_PC (regno, newval);
106 crisv10f_h_gr_real_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
108 CPU (h_gr_real_pc[regno]) = newval;
[all...] |
| /src/external/gpl3/gdb/dist/sim/cris/ |
| cpuv32.c | 42 crisv32f_h_v32_v32_set (SIM_CPU *current_cpu, BI newval)
44 SET_H_V32_V32 (newval);
58 crisv32f_h_pc_set (SIM_CPU *current_cpu, USI newval)
60 SET_H_PC (newval);
74 crisv32f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
76 SET_H_GR (regno, newval);
90 crisv32f_h_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
92 CPU (h_gr_acr[regno]) = newval;
106 crisv32f_h_raw_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
108 SET_H_RAW_GR_ACR (regno, newval);
[all...] |
| cpuv10.c | 42 crisv10f_h_v32_non_v32_set (SIM_CPU *current_cpu, BI newval)
44 SET_H_V32_NON_V32 (newval);
58 crisv10f_h_pc_set (SIM_CPU *current_cpu, USI newval)
60 SET_H_PC (newval);
74 crisv10f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
76 SET_H_GR (regno, newval);
90 crisv10f_h_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
92 SET_H_GR_PC (regno, newval);
106 crisv10f_h_gr_real_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
108 CPU (h_gr_real_pc[regno]) = newval;
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/m32r/ |
| cpu2.c | 42 m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 CPU (h_pc) = newval;
58 m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 CPU (h_gr[regno]) = newval;
74 m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
76 SET_H_CR (regno, newval);
90 m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval)
92 SET_H_ACCUM (newval);
106 m32r2f_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
108 SET_H_ACCUMS (regno, newval);
[all...] |
| cpux.c | 42 m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 CPU (h_pc) = newval;
58 m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 CPU (h_gr[regno]) = newval;
74 m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
76 SET_H_CR (regno, newval);
90 m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
92 SET_H_ACCUM (newval);
106 m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
108 SET_H_ACCUMS (regno, newval);
[all...] |
| cpu.c | 42 m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 CPU (h_pc) = newval;
58 m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 CPU (h_gr[regno]) = newval;
74 m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
76 SET_H_CR (regno, newval);
90 m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
92 SET_H_ACCUM (newval);
106 m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval)
108 CPU (h_cond) = newval;
[all...] |
| /src/external/gpl3/gdb/dist/sim/m32r/ |
| cpu2.c | 42 m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 CPU (h_pc) = newval;
58 m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 CPU (h_gr[regno]) = newval;
74 m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
76 SET_H_CR (regno, newval);
90 m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval)
92 SET_H_ACCUM (newval);
106 m32r2f_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
108 SET_H_ACCUMS (regno, newval);
[all...] |
| cpux.c | 42 m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 CPU (h_pc) = newval;
58 m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 CPU (h_gr[regno]) = newval;
74 m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
76 SET_H_CR (regno, newval);
90 m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
92 SET_H_ACCUM (newval);
106 m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
108 SET_H_ACCUMS (regno, newval);
[all...] |
| cpu.c | 42 m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 CPU (h_pc) = newval;
58 m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 CPU (h_gr[regno]) = newval;
74 m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
76 SET_H_CR (regno, newval);
90 m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
92 SET_H_ACCUM (newval);
106 m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval)
108 CPU (h_cond) = newval;
[all...] |
| /src/external/gpl3/gcc/dist/libgomp/config/nvptx/ |
| atomic.c | 11 unsigned __int128 newval)
15 __atomic_compare_exchange_n (ptr, &expected, newval, false,
|
| /src/external/gpl3/gcc.old/dist/libgomp/config/nvptx/ |
| atomic.c | 11 unsigned __int128 newval)
15 __atomic_compare_exchange_n (ptr, &expected, newval, false,
|
| /src/external/gpl3/gdb.old/dist/sim/iq2000/ |
| cpu.c | 42 iq2000bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 SET_H_PC (newval);
58 iq2000bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 SET_H_GR (regno, newval);
|
| /src/external/gpl3/gdb/dist/sim/iq2000/ |
| cpu.c | 42 iq2000bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 SET_H_PC (newval);
58 iq2000bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 SET_H_GR (regno, newval);
|
| /src/external/gpl3/gdb.old/dist/sim/frv/ |
| cpu.c | 42 frvbf_h_reloc_ann_set (SIM_CPU *current_cpu, BI newval)
44 CPU (h_reloc_ann) = newval;
58 frvbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
60 CPU (h_pc) = newval;
74 frvbf_h_psr_imple_set (SIM_CPU *current_cpu, UQI newval)
76 CPU (h_psr_imple) = newval;
90 frvbf_h_psr_ver_set (SIM_CPU *current_cpu, UQI newval)
92 CPU (h_psr_ver) = newval;
106 frvbf_h_psr_ice_set (SIM_CPU *current_cpu, BI newval)
108 CPU (h_psr_ice) = newval;
[all...] |
| /src/external/gpl3/gdb/dist/sim/frv/ |
| cpu.c | 42 frvbf_h_reloc_ann_set (SIM_CPU *current_cpu, BI newval)
44 CPU (h_reloc_ann) = newval;
58 frvbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
60 CPU (h_pc) = newval;
74 frvbf_h_psr_imple_set (SIM_CPU *current_cpu, UQI newval)
76 CPU (h_psr_imple) = newval;
90 frvbf_h_psr_ver_set (SIM_CPU *current_cpu, UQI newval)
92 CPU (h_psr_ver) = newval;
106 frvbf_h_psr_ice_set (SIM_CPU *current_cpu, BI newval)
108 CPU (h_psr_ice) = newval;
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/lm32/ |
| cpu.c | 42 lm32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 CPU (h_pc) = newval;
58 lm32bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 CPU (h_gr[regno]) = newval;
74 lm32bf_h_csr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
76 CPU (h_csr[regno]) = newval;
|
| /src/external/mit/libuv/dist/src/unix/ |
| atomic-ops.h | 25 UV_UNUSED(static int cmpxchgi(int* ptr, int oldval, int newval));
31 UV_UNUSED(static int cmpxchgi(int* ptr, int oldval, int newval)) {
36 : "r" (newval), "0" (oldval)
43 __asm(" cs %0,%2,%1 \n " : "+r"(oldval), "+m"(*ptr) : "r"(newval) :);
46 return atomic_cas_uint((uint_t *)ptr, (uint_t)oldval, (uint_t)newval);
48 return __sync_val_compare_and_swap(ptr, oldval, newval);
|
| /src/external/gpl3/gdb/dist/sim/lm32/ |
| cpu.c | 42 lm32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
44 CPU (h_pc) = newval;
58 lm32bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
60 CPU (h_gr[regno]) = newval;
74 lm32bf_h_csr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
76 CPU (h_csr[regno]) = newval;
|
| /src/external/gpl3/gcc/dist/libgcc/config/m68k/ |
| linux-atomic.c | 44 __kernel_cmpxchg (unsigned *mem, unsigned oldval, unsigned newval)
48 register unsigned d1 asm("d1") = newval;
75 unsigned oldval, newval, cmpval = *ptr; \
79 newval = PFX_OP (oldval INF_OP val); \
80 cmpval = __kernel_cmpxchg (ptr, oldval, newval); \
91 unsigned int mask, shift, oldval, newval, cmpval, wval; \
100 newval = PFX_OP (oldval INF_OP wval); \
101 newval = (newval & mask) | (oldval & ~mask); \
102 cmpval = __kernel_cmpxchg (wordptr, oldval, newval); \
[all...] |
| /src/external/gpl3/gcc.old/dist/libgcc/config/m68k/ |
| linux-atomic.c | 44 __kernel_cmpxchg (unsigned *mem, unsigned oldval, unsigned newval)
48 register unsigned d1 asm("d1") = newval;
75 unsigned oldval, newval, cmpval = *ptr; \
79 newval = PFX_OP (oldval INF_OP val); \
80 cmpval = __kernel_cmpxchg (ptr, oldval, newval); \
91 unsigned int mask, shift, oldval, newval, cmpval, wval; \
100 newval = PFX_OP (oldval INF_OP wval); \
101 newval = (newval & mask) | (oldval & ~mask); \
102 cmpval = __kernel_cmpxchg (wordptr, oldval, newval); \
[all...] |
| /src/sys/arch/zaurus/dev/ |
| lcdctlvar.h | 31 void lcdctl_brightness(int newval);
|
| /src/common/lib/libc/atomic/ |
| atomic_cas_16_cas.c | 44 uint16_t newval, ...)
46 return atomic_cas_16(addr, oldval, newval) == oldval;
|
