| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_pp_smu.c | 136 clks->num_levels = 6;
141 clks->num_levels = 6;
146 clks->num_levels = 2;
151 clks->num_levels = 0;
268 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
270 dc_clks->num_levels = pp_clks->count;
275 for (i = 0; i < dc_clks->num_levels; i++) {
288 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
291 pp_clks->num_levels,
294 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_resource.c | 909 &eng_clks) || eng_clks.num_levels == 0) {
911 eng_clks.num_levels = 8;
914 for (i = 0; i < eng_clks.num_levels; i++) {
922 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
924 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
926 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
928 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
930 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
932 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
934 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 1061 clks.clocks_in_khz[clks.num_levels-1], 1000);
1063 clks.clocks_in_khz[clks.num_levels/8], 1000);
1065 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1067 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1069 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1071 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1073 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1086 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1089 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1097 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 100 uint32_t num_levels; member in struct:dm_pp_clock_levels
110 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_latency
120 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_voltage
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| dm_pp_interface.h | 177 uint32_t num_levels; member in struct:pp_clock_levels_with_latency
187 uint32_t num_levels; member in struct:pp_clock_levels_with_voltage
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| r100_track.h | 46 unsigned num_levels; member in struct:r100_cs_track_texture
|
| radeon_sumo_dpm.c | 352 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
359 for (i = 0; i < ps->num_levels - 1; i++)
413 for (i = 0; i < ps->num_levels; i++) {
414 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
428 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
429 CG_L(m_a * l[ps->num_levels - 1] / 100);
675 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
748 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
764 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
766 for (i = 0; i < new_ps->num_levels; i++)
[all...] |
| trinity_dpm.h | 50 u32 num_levels; member in struct:trinity_ps
|
| radeon_trinity_dpm.c | 851 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
853 for (i = 0; i < new_ps->num_levels; i++) {
858 for (i = new_ps->num_levels; i < n_current_state_levels; i++)
974 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
975 current_ps->levels[current_ps->num_levels - 1].sclk)
988 if (new_ps->levels[new_ps->num_levels - 1].sclk <
989 current_ps->levels[current_ps->num_levels - 1].sclk)
1214 if (ps->num_levels <= 1)
1221 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1);
1225 for (i = 0; i < ps->num_levels; i++)
[all...] |
| kv_dpm.h | 85 u32 num_levels; member in struct:kv_ps
|
| sumo_dpm.h | 49 u32 num_levels; member in struct:sumo_ps
|
| radeon_kv_dpm.c | 1732 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1739 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1758 new_ps->levels[new_ps->num_levels - 1].sclk)
1767 new_ps->levels[new_ps->num_levels -1].sclk))
2195 for (i = 0; i < ps->num_levels; i++) {
2201 for (i = 0; i < ps->num_levels; i++) {
2213 for (i = 0; i < ps->num_levels; i++) {
2224 for (i = 0; i < ps->num_levels; i++) {
2586 ps->num_levels = 1;
2631 ps->num_levels = index + 1
[all...] |
| radeon_r200.c | 424 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 81 if (dc->sclk_lvls.num_levels == 0)
84 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
94 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 1268 clks.clocks_in_khz[clks.num_levels-1], 1000);
1270 clks.clocks_in_khz[clks.num_levels/8], 1000);
1272 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1274 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1276 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1278 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1280 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1291 clks.clocks_in_khz[clks.num_levels-1], 1000);
1293 clks.clocks_in_khz[clks.num_levels>>1], 1000);
1306 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu10_hwmgr.c | 1034 clocks->num_levels = 0;
1037 clocks->data[clocks->num_levels].clocks_in_khz =
1039 clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1043 clocks->num_levels++;
1088 clocks->num_levels = 0;
1091 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
1092 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;
1093 clocks->num_levels++;
|
| amdgpu_vega12_hwmgr.c | 1737 clocks->num_levels = ucount;
1770 clocks->num_levels = data->mclk_latency_table.count = ucount;
1798 clocks->num_levels = ucount;
1826 clocks->num_levels = ucount;
1862 clocks->num_levels = 0;
2109 for (i = 0; i < clocks.num_levels; i++)
2125 for (i = 0; i < clocks.num_levels; i++)
2143 for (i = 0; i < clocks.num_levels; i++)
2161 for (i = 0; i < clocks.num_levels; i++)
|
| amdgpu_vega20_hwmgr.c | 2775 clocks->num_levels = count;
2803 clocks->num_levels = data->mclk_latency_table.count = count;
2828 clocks->num_levels = count;
2850 clocks->num_levels = count;
2892 clocks->num_levels = 0;
3292 for (i = 0; i < clocks.num_levels; i++)
3310 for (i = 0; i < clocks.num_levels; i++)
3328 for (i = 0; i < clocks.num_levels; i++)
3358 for (i = 0; i < clocks.num_levels; i++)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| kv_dpm.h | 111 u32 num_levels; member in struct:kv_ps
|
| amdgpu_kv_dpm.c | 1796 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1803 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1822 new_ps->levels[new_ps->num_levels - 1].sclk)
1831 new_ps->levels[new_ps->num_levels -1].sclk))
2260 for (i = 0; i < ps->num_levels; i++) {
2266 for (i = 0; i < ps->num_levels; i++) {
2278 for (i = 0; i < ps->num_levels; i++) {
2289 for (i = 0; i < ps->num_levels; i++) {
2654 ps->num_levels = 1;
2699 ps->num_levels = index + 1
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 1427 if (clks->num_levels == 0)
1430 for (i = 0; i < clks->num_levels; i++)
1455 ASSERT(fclks.num_levels);
1458 vmid0p72_idx = fclks.num_levels -
1459 (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1));
1460 vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1);
1461 vmax0p9_idx = fclks.num_levels - 1;
1490 if (res && dcfclks.num_levels >= 3)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_debugfs.c | 3230 int num_levels; local in function:wm_latency_show
3233 num_levels = 3;
3235 num_levels = 1;
3237 num_levels = 3;
3239 num_levels = ilk_wm_max_level(dev_priv) + 1;
3243 for (level = 0; level < num_levels; level++) {
3347 int num_levels; local in function:wm_latency_write
3353 num_levels = 3;
3355 num_levels = 1;
3357 num_levels = 3
[all...] |
| intel_pm.c | 1226 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); local in function:g4x_raw_plane_wm_compute
1238 for (level = 0; level < num_levels; level++) {
1790 int num_levels = intel_wm_num_levels(dev_priv); local in function:vlv_raw_plane_wm_set
1793 for (; level < num_levels; level++) {
1809 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); local in function:vlv_raw_plane_wm_compute
1818 for (level = 0; level < num_levels; level++) {
1924 wm_state->num_levels = intel_wm_num_levels(dev_priv);
1932 for (level = 0; level < wm_state->num_levels; level++) {
1960 wm_state->num_levels = level;
2088 intermediate->num_levels = min(optimal->num_levels, active->num_levels)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_arcturus_ppt.c | 603 clocks->num_levels = count;
655 for (i = 0; i < clocks.num_levels; i++)
658 (clocks.num_levels == 1) ? "*" :
678 for (i = 0; i < clocks.num_levels; i++)
681 (clocks.num_levels == 1) ? "*" :
701 for (i = 0; i < clocks.num_levels; i++)
704 (clocks.num_levels == 1) ? "*" :
727 (clocks.num_levels == 1) ? "*" :
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 583 if (dc->sclk_lvls.num_levels == 0)
586 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
596 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
|
