| /src/sbin/luactl/ |
| luactl.c | 129 if (info.num_states > 0) {
130 info.states = calloc(info.num_states,
137 printf("%d active state%s:\n", info.num_states,
138 info.num_states == 1 ? "" : "s");
139 if (info.num_states > 0)
141 for (n = 0; n < info.num_states; n++)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_socbb.h | 80 uint32_t num_states; member in struct:gpu_info_soc_bounding_box_v1_0
|
| /src/sys/sys/ |
| lua.h | 56 int num_states; /* total number of created Lua states */ member in struct:lua_info
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_pp_smu.h | 231 unsigned int *clock_values_in_khz, unsigned int *num_states);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_resource.h | 105 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
|
| amdgpu_dcn20_resource.c | 302 .num_states = 5,
2502 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2506 if (vlevel > context->bw_ctx.dml.soc.num_states)
2575 if (vlevel > context->bw_ctx.dml.soc.num_states)
2643 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2918 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3147 for (i = 0; i < bb->num_states; i++) {
3182 for (i = bb->num_states - 1; i > 1; i--) {
3203 bb->num_states--;
3208 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3448 unsigned int num_states = 0; local in function:init_soc_bounding_box
[all...] |
| /src/sys/modules/lua/ |
| lua.c | 305 info->num_states = 0;
307 info->num_states++;
311 if (n > info->num_states)
315 info->num_states = n;
321 if (n > info->num_states)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| display_mode_structs.h | 114 unsigned int num_states; member in struct:_vcs_dpi_soc_bounding_box_st
|
| amdgpu_display_mode_vba.c | 243 for (i = 0; i < mode_lib->vba.soc.num_states; i++)
261 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
275 mode_lib->vba.MaxVoltageLevel = mode_lib->vba.soc.num_states;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_mode_vba_20v2.c | 1325 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
2640 for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
3482 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3564 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3915 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3917 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
3934 && i == mode_lib->vba.soc.num_states)
3941 && i == mode_lib->vba.soc.num_states)
4018 if (i != mode_lib->vba.soc.num_states) {
4050 for (i = 0; i <= mode_lib->vba.soc.num_states; i++)
[all...] |
| amdgpu_display_mode_vba_20.c | 1265 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
2603 for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
3445 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3527 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3878 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3893 && i == mode_lib->vba.soc.num_states)
3900 && i == mode_lib->vba.soc.num_states)
3974 if (i != mode_lib->vba.soc.num_states) {
4006 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4023 for (i = 0; i <= mode_lib->vba.soc.num_states; i++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_mode_vba_21.c | 1644 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz,
3550 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3592 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3946 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3948 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
3970 && i == mode_lib->vba.soc.num_states)
3977 && i == mode_lib->vba.soc.num_states)
4054 if (i != mode_lib->vba.soc.num_states) {
4086 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4103 for (i = 0; i <= mode_lib->vba.soc.num_states; i++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 274 .num_states = 5
988 ASSERT(vlevel < dml->soc.num_states);
1168 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1358 dcn2_1_soc.num_states = i;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_pp_smu.c | 881 unsigned int *clock_values_in_khz, unsigned int *num_states)
894 clock_values_in_khz, num_states))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| amdgpu_smu.h | 480 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
739 unsigned int *num_states);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_navi10_ppt.c | 1634 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1642 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1652 *num_states = num_discrete_levels;
|
| amdgpu_smu.c | 2581 unsigned int *num_states)
2588 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
|
