| /src/sys/arch/powerpc/pci/ |
| pciconf_indirect.c | 110 out32rb(pc->pc_addr, tag | reg);
112 out32rb(pc->pc_addr, 0);
128 out32rb(pc->pc_addr, tag | reg);
129 out32rb(pc->pc_data, data);
130 out32rb(pc->pc_addr, 0);
|
| pchb.c | 266 out32rb(python+0x30, v);
|
| /src/sys/arch/macppc/macppc/ |
| pic_heathrow.c | 131 out32rb(INT_ENABLE_REG_L, 0);
132 out32rb(INT_CLEAR_REG_L, 0xffffffff);
133 out32rb(INT_ENABLE_REG_H, 0);
134 out32rb(INT_CLEAR_REG_H, 0xffffffff);
146 out32rb(INT_ENABLE_REG_H, heathrow->enable_mask_h);
149 out32rb(INT_ENABLE_REG_L, heathrow->enable_mask_l);
162 out32rb(INT_ENABLE_REG_H, heathrow->enable_mask_h);
166 out32rb(INT_CLEAR_REG_H, mask);
170 out32rb(INT_ENABLE_REG_L, heathrow->enable_mask_l);
174 out32rb(INT_CLEAR_REG_L, mask)
[all...] |
| pic_ohare.c | 148 out32rb(INT_ENABLE_REG, 0);
149 out32rb(INT_CLEAR_REG, 0xffffffff);
171 out32rb(INT_ENABLE_REG, ohare->enable_mask);
182 out32rb(INT_ENABLE_REG, ohare->enable_mask);
186 out32rb(INT_CLEAR_REG, mask);
197 out32rb(INT_ENABLE_REG, ohare->enable_mask);
211 out32rb(INT_CLEAR_REG, events | irqs);
|
| pic_u3_ht.c | 362 out32rb(base + 0x04, tmp);
499 out32rb(irqmap->im_base + 0x04, x | HTAPIC_MASK);
512 out32rb(irqmap->im_base + 0x04, x);
524 out32rb(irqmap->im_base + 0x04, x);
538 out32rb(irqmap->im_base + 0x04, x);
548 out32rb(irqmap->im_apple_base + ((irqmap->im_index >> 3) & ~0x03),
552 out32rb(irqmap->im_base + 0x04, irqmap->im_data);
618 out32rb(addr, val);
|
| /src/sys/arch/rs6000/rs6000/ |
| pic_iocc.c | 108 out32rb(RS6000_BUS_SPACE_IO + IOCC_IEE, mask);
119 out32rb(RS6000_BUS_SPACE_IO + IOCC_IEE, mask);
126 out32rb(RS6000_BUS_SPACE_IO + IOCC_EOI(irq), 0x1); /* val is ignored */
137 out32rb(RS6000_BUS_SPACE_IO + IOCC_XIVR(irq), x);
|
| /src/sys/arch/macppc/dev/ |
| mediabay.c | 181 out32rb(sc->sc_fcr, fcr);
185 out32rb(sc->sc_fcr, fcr);
189 out32rb(sc->sc_fcr, fcr);
197 out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_RESET);
198 out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_POWER);
201 out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_ENABLE);
204 out32rb(sc->sc_addr,
208 out32rb(sc->sc_addr, in32rb(sc->sc_addr) | MBCR_MEDIABAY0_RESET);
211 out32rb(sc->sc_fcr, in32rb(sc->sc_fcr) | FCR1_EIDE0_RESET);
212 out32rb(sc->sc_fcr, in32rb(sc->sc_fcr) | FCR1_EIDE0_ENABLE)
[all...] |
| dbdma.c | 71 out32rb(&dmap->d_control, DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_RUN) |
81 out32rb(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH));
89 out32rb(&dmap->d_control,
103 out32rb(&dmap->d_control,
|
| dbdma.h | 122 out32rb(&(d)->d_address, address); \
133 #define DBDMA_ST4_ENDIAN(a, x) out32rb(a, x)
|
| if_mc.c | 319 out32rb(&cmd->d_cmddep, kvtop((void *)sc->sc_rxdmacmd));
349 out32rb(&dmareg->d_cmdptrhi, 0);
350 out32rb(&dmareg->d_cmdptrlo, kvtop((void *)sc->sc_txdmacmd));
|
| /src/sys/arch/evbppc/ev64260/ |
| machdep.c | 301 out32rb(gt_base + GTMPSC_MRR, GTMPSC_MRR_RES);
305 out32rb(gt_base + GTMPSC_RCRR, cr);
306 out32rb(gt_base + GTMPSC_TCRR, cr);
309 out32rb(gt_base + BRG_BCR(brg),
418 out32rb(gt_base + GT_PCI0_Mem0_Low_Decode, datal);
423 out32rb(gt_base + GT_PCI0_Mem0_High_Decode, datal);
444 out32rb(gt_base + GT_PCI1_IO_Remap, 0);
451 out32rb(gt_base + GT_PCI0_IO_Low_Decode, datal);
456 out32rb(gt_base + GT_PCI0_IO_High_Decode, datal);
471 out32rb(gt_base + GT_PCI1_Mem0_Low_Decode, datal)
[all...] |
| /src/sys/arch/macppc/pci/ |
| grackle.c | 164 out32rb(pc->pc_addr, tag | reg);
168 out32rb(pc->pc_addr, 0);
186 out32rb(pc->pc_addr, tag | reg);
187 out32rb(pc->pc_data, data);
188 out32rb(pc->pc_addr, 0);
|
| uninorth.c | 224 out32rb(pc->pc_addr, x);
229 out32rb(pc->pc_addr, 0);
265 out32rb(pc->pc_addr, x);
267 out32rb(daddr, data);
268 out32rb(pc->pc_addr, 0);
302 out32rb(pc->pc_addr, x);
308 out32rb(pc->pc_addr, 0);
342 out32rb(pc->pc_addr, x);
344 out32rb(daddr, data);
345 out32rb(pc->pc_addr, 0)
[all...] |
| bandit.c | 188 out32rb(pc->pc_addr, x);
194 out32rb(pc->pc_addr, 0);
226 out32rb(pc->pc_addr, x);
228 out32rb(pc->pc_data, data);
230 out32rb(pc->pc_addr, 0);
|
| u3.c | 243 out32rb(x, data);
|
| /src/sys/arch/powerpc/include/ |
| openpic.h | 53 out32rb(addr, val);
|
| pio.h | 177 #define out32rb(a,v) outlrb(a,v) macro
|
| /src/sys/arch/ibmnws/ibmnws/ |
| machdep.c | 102 out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK0_START);
105 out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK0_END);
109 out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK_ENABLE);
113 out32rb(PCI_MODE1_ADDRESS_REG, 0);
|
| /src/sys/arch/sandpoint/pci/ |
| pci_machdep.c | 219 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg);
221 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);
232 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg);
233 out32rb(SANDPOINT_PCI_CONFIG_DATA, data);
234 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);
|
| /src/sys/arch/sandpoint/stand/altboot/ |
| entry.S | 235 .globl out32rb
237 out32rb: label
|
| globals.h | 63 void out32rb(unsigned, unsigned);
|
| siisata.c | 42 #define CSR_WRITE_4(r,v) out32rb(r,v)
|
| /src/sys/arch/sandpoint/sandpoint/ |
| machdep.c | 527 out32rb(0xfec00000, (1U<<31) | MPC107_MEMEN);
541 out32rb(0xfec00000, (1U<<31) | MPC107_EXTMEMENDADDR1); /* bit 29:28 */
544 out32rb(0xfec00000, (1U<<31) | MPC107_MEMENDADDR1); /* bit 27:20 */
|
| /src/sys/arch/prep/pci/ |
| prep_pciconf_direct.c | 219 out32rb(PCI_DCONF_BASE | tag | reg, data);
|
| /src/sys/arch/powerpc/pic/ |
| pic_distopenpic.c | 167 out32rb(addr, val);
|
