1 /* $NetBSD: if_mc.c,v 1.28 2022/02/16 23:49:26 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym (at) bga.com> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1 (at) home.com> 8 * and Yanagisawa Takeshi <yanagisw (at) aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_mc.c,v 1.28 2022/02/16 23:49:26 riastradh Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/socket.h> 45 #include <sys/systm.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <dev/ofw/openfirm.h> 52 53 #include <sys/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/pio.h> 56 57 #include <macppc/dev/am79c950reg.h> 58 #include <macppc/dev/if_mcvar.h> 59 60 #define MC_BUFSIZE 0x800 61 62 hide int mc_match(device_t, cfdata_t, void *); 63 hide void mc_attach(device_t, device_t, void *); 64 hide void mc_init(struct mc_softc *); 65 hide void mc_putpacket(struct mc_softc *, u_int); 66 hide int mc_dmaintr(void *); 67 hide void mc_reset_rxdma(struct mc_softc *); 68 hide void mc_reset_txdma(struct mc_softc *); 69 hide void mc_select_utp(struct mc_softc *); 70 hide void mc_select_aui(struct mc_softc *); 71 hide int mc_mediachange(struct mc_softc *); 72 hide void mc_mediastatus(struct mc_softc *, struct ifmediareq *); 73 74 int mc_supmedia[] = { 75 IFM_ETHER | IFM_10_T, 76 IFM_ETHER | IFM_10_5, 77 /*IFM_ETHER | IFM_AUTO,*/ 78 }; 79 80 #define N_SUPMEDIA __arraycount(mc_supmedia) 81 82 CFATTACH_DECL_NEW(mc, sizeof(struct mc_softc), 83 mc_match, mc_attach, NULL, NULL); 84 85 hide int 86 mc_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 struct confargs *ca = aux; 89 90 if (strcmp(ca->ca_name, "mace") != 0) 91 return 0; 92 93 /* requires 6 regs */ 94 if (ca->ca_nreg / sizeof(int) != 6) 95 return 0; 96 97 /* requires 3 intrs */ 98 if (ca->ca_nintr / sizeof(int) != 3) 99 return 0; 100 101 return 1; 102 } 103 104 hide void 105 mc_attach(device_t parent, device_t self, void *aux) 106 { 107 struct confargs *ca = aux; 108 struct mc_softc *sc = device_private(self); 109 uint8_t myaddr[ETHER_ADDR_LEN]; 110 u_int *reg; 111 char intr_xname[INTRDEVNAMEBUF]; 112 113 sc->sc_dev = self; 114 sc->sc_node = ca->ca_node; 115 sc->sc_regt = ca->ca_tag; 116 117 reg = ca->ca_reg; 118 reg[0] += ca->ca_baseaddr; 119 reg[2] += ca->ca_baseaddr; 120 reg[4] += ca->ca_baseaddr; 121 122 sc->sc_txdma = mapiodev(reg[2], reg[3], false); 123 sc->sc_rxdma = mapiodev(reg[4], reg[5], false); 124 bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh); 125 126 sc->sc_tail = 0; 127 sc->sc_txdmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 2, NULL); 128 sc->sc_rxdmacmd = (void *)dbdma_alloc(sizeof(dbdma_command_t) * 8, 129 NULL); 130 memset(sc->sc_txdmacmd, 0, sizeof(dbdma_command_t) * 2); 131 memset(sc->sc_rxdmacmd, 0, sizeof(dbdma_command_t) * 8); 132 133 printf(": irq %d,%d,%d", 134 ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]); 135 136 if (OF_getprop(sc->sc_node, "local-mac-address", myaddr, 6) != 6) { 137 printf(": failed to get MAC address.\n"); 138 return; 139 } 140 141 /* Allocate memory for transmit buffer and mark it non-cacheable */ 142 sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK); 143 sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); 144 memset(sc->sc_txbuf, 0, PAGE_SIZE); 145 146 /* 147 * Allocate memory for receive buffer and mark it non-cacheable 148 * XXX This should use the bus_dma interface, since the buffer 149 * needs to be physically contiguous. However, it seems that 150 * at least on my system, malloc() does allocate contiguous 151 * memory. If it's not, suggest reducing the number of buffers 152 * to 2, which will fit in one 4K page. 153 */ 154 sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK); 155 sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); 156 memset(sc->sc_rxbuf, 0, MC_NPAGES * PAGE_SIZE); 157 158 if ((int)sc->sc_txbuf & PGOFSET) 159 printf("txbuf is not page-aligned\n"); 160 if ((int)sc->sc_rxbuf & PGOFSET) 161 printf("rxbuf is not page-aligned\n"); 162 163 sc->sc_bus_init = mc_init; 164 sc->sc_putpacket = mc_putpacket; 165 166 /* Disable receive DMA */ 167 dbdma_reset(sc->sc_rxdma); 168 169 /* Disable transmit DMA */ 170 dbdma_reset(sc->sc_txdma); 171 172 /* Install interrupt handlers */ 173 174 /*intr_establish(ca->ca_intr[1], IST_EDGE, IPL_NET, mc_dmaintr, sc);*/ 175 176 snprintf(intr_xname, sizeof(intr_xname), "%s dma", device_xname(self)); 177 intr_establish_xname(ca->ca_intr[2], IST_EDGE, IPL_NET, mc_dmaintr, sc, 178 intr_xname); 179 180 snprintf(intr_xname, sizeof(intr_xname), "%s pio", device_xname(self)); 181 intr_establish_xname(ca->ca_intr[0], IST_EDGE, IPL_NET, mcintr, sc, 182 intr_xname); 183 184 sc->sc_biucc = XMTSP_64; 185 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 186 XMTBRST | RCVBRST; 187 /*sc->sc_plscc = PORTSEL_10BT;*/ 188 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 189 190 /* mcsetup returns 1 if something fails */ 191 if (mcsetup(sc, myaddr)) { 192 printf("mcsetup returns non zero\n"); 193 return; 194 } 195 #ifdef NOTYET 196 sc->sc_mediachange = mc_mediachange; 197 sc->sc_mediastatus = mc_mediastatus; 198 sc->sc_supmedia = mc_supmedia; 199 sc->sc_nsupmedia = N_SUPMEDIA; 200 sc->sc_defaultmedia = IFM_ETHER | IFM_10_T; 201 #endif 202 } 203 204 /* Bus-specific initialization */ 205 hide void 206 mc_init(struct mc_softc *sc) 207 { 208 mc_reset_rxdma(sc); 209 mc_reset_txdma(sc); 210 } 211 212 hide void 213 mc_putpacket(struct mc_softc *sc, u_int len) 214 { 215 dbdma_command_t *cmd = sc->sc_txdmacmd; 216 217 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_phys, 218 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 219 220 dbdma_start(sc->sc_txdma, sc->sc_txdmacmd); 221 } 222 223 /* 224 * Interrupt handler for the MACE DMA completion interrupts 225 */ 226 int 227 mc_dmaintr(void *arg) 228 { 229 struct mc_softc *sc = arg; 230 int status, offset, statoff; 231 int datalen, resid; 232 int i, n; 233 dbdma_command_t *cmd; 234 235 /* We've received some packets from the MACE */ 236 237 /* Loop through, processing each of the packets */ 238 i = sc->sc_tail; 239 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 240 if (i == MC_RXDMABUFS) 241 i = 0; 242 243 cmd = &sc->sc_rxdmacmd[i]; 244 /* flushcache(cmd, sizeof(dbdma_command_t)); */ 245 status = in16rb(&cmd->d_status); 246 resid = in16rb(&cmd->d_resid); 247 248 /*if ((status & D_ACTIVE) == 0)*/ 249 if ((status & 0x40) == 0) 250 continue; 251 252 #if 1 253 if (in16rb(&cmd->d_count) != ETHERMTU + 22) 254 printf("bad d_count\n"); 255 #endif 256 257 datalen = in16rb(&cmd->d_count) - resid; 258 datalen -= 4; /* 4 == status bytes */ 259 260 if (datalen < 4 + sizeof(struct ether_header)) { 261 printf("short packet len=%d\n", datalen); 262 /* continue; */ 263 goto next; 264 } 265 266 offset = i * MC_BUFSIZE; 267 statoff = offset + datalen; 268 269 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 270 __asm volatile("eieio" ::: "memory"); 271 272 /* flushcache(sc->sc_rxbuf + offset, datalen + 4); */ 273 274 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 275 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 276 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 277 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 278 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 279 280 mc_rint(sc); 281 282 next: 283 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 284 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 285 __asm volatile("eieio" ::: "memory"); 286 cmd->d_status = 0; 287 cmd->d_resid = 0; 288 sc->sc_tail = i + 1; 289 } 290 291 dbdma_continue(sc->sc_rxdma); 292 293 return 1; 294 } 295 296 hide void 297 mc_reset_rxdma(struct mc_softc *sc) 298 { 299 dbdma_command_t *cmd = sc->sc_rxdmacmd; 300 dbdma_regmap_t *dmareg = sc->sc_rxdma; 301 int i; 302 uint8_t maccc; 303 304 /* Disable receiver, reset the DMA channels */ 305 maccc = NIC_GET(sc, MACE_MACCC); 306 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 307 308 dbdma_reset(dmareg); 309 310 for (i = 0; i < MC_RXDMABUFS; i++) { 311 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, ETHERMTU + 22, 312 sc->sc_rxbuf_phys + MC_BUFSIZE * i, DBDMA_INT_ALWAYS, 313 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 314 cmd++; 315 } 316 317 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 318 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 319 out32rb(&cmd->d_cmddep, kvtop((void *)sc->sc_rxdmacmd)); 320 cmd++; 321 322 dbdma_start(dmareg, sc->sc_rxdmacmd); 323 324 sc->sc_tail = 0; 325 326 /* Reenable receiver, reenable DMA */ 327 NIC_PUT(sc, MACE_MACCC, maccc); 328 } 329 330 hide void 331 mc_reset_txdma(struct mc_softc *sc) 332 { 333 dbdma_command_t *cmd = sc->sc_txdmacmd; 334 dbdma_regmap_t *dmareg = sc->sc_txdma; 335 uint8_t maccc; 336 337 /* Disable transmitter */ 338 maccc = NIC_GET(sc, MACE_MACCC); 339 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 340 341 dbdma_reset(dmareg); 342 343 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_phys, 344 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 345 cmd++; 346 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 347 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 348 349 out32rb(&dmareg->d_cmdptrhi, 0); 350 out32rb(&dmareg->d_cmdptrlo, kvtop((void *)sc->sc_txdmacmd)); 351 352 /* Restore old value */ 353 NIC_PUT(sc, MACE_MACCC, maccc); 354 } 355 356 void 357 mc_select_utp(struct mc_softc *sc) 358 { 359 360 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 361 } 362 363 void 364 mc_select_aui(struct mc_softc *sc) 365 { 366 367 sc->sc_plscc = PORTSEL_AUI; 368 } 369 370 int 371 mc_mediachange(struct mc_softc *sc) 372 { 373 struct ifmedia *ifm = &sc->sc_media; 374 375 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 376 return EINVAL; 377 378 switch (IFM_SUBTYPE(ifm->ifm_media)) { 379 380 case IFM_10_T: 381 mc_select_utp(sc); 382 break; 383 384 case IFM_10_5: 385 mc_select_aui(sc); 386 break; 387 388 default: 389 return EINVAL; 390 } 391 392 return 0; 393 } 394 395 void 396 mc_mediastatus(struct mc_softc *sc, struct ifmediareq *ifmr) 397 { 398 399 if (sc->sc_plscc == PORTSEL_AUI) 400 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 401 else 402 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 403 } 404
Indexes created Sun Sep 21 20:09:37 GMT 2025