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    Searched refs:parent_rate (Results 1 - 25 of 26) sorted by relevancy

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  /src/sys/arch/arm/amlogic/
meson_clk_mpll.c 47 uint64_t parent_rate, sdm, n2; local
57 parent_rate = clk_get_rate(clkp_parent);
58 if (parent_rate == 0)
75 return (u_int)howmany(parent_rate * SDM_DEN, div);
meson_clk_pll.c 46 uint64_t parent_rate, rate; local
56 parent_rate = clk_get_rate(clkp_parent);
57 if (parent_rate == 0)
77 rate = parent_rate * m;
79 uint64_t frac_rate = parent_rate * frac;
104 uint64_t parent_rate, tmp; local
118 parent_rate = clk_get_rate(clkp_parent);
119 if (parent_rate == 0) {
124 if (parent_rate > new_rate) {
125 n = parent_rate / new_rate
    [all...]
meson_clk_div.c 85 int parent_rate; local
106 parent_rate = clk_get_rate(clkp_parent);
107 if (parent_rate == 0) {
112 ratio = howmany(parent_rate, new_rate);
meson8b_clkc.c 116 const u_int parent_rate = clk_get_rate(clkp_parent); local
117 if (parent_rate == 0)
125 u_int new_mul = rate / parent_rate;
161 delay((100 * old_rate) / parent_rate);
mesongx_mmc.c 482 const u_int parent_rate = clk_get_rate(sc->sc_clk_clkin[sel]); local
484 const u_int rate = parent_rate / div;
  /src/sys/arch/arm/sunxi/
sunxi_ccu_fractional.c 110 u_int parent_rate, best_rate, best_m; local
121 parent_rate = clk_get_rate(clkp_parent);
122 if (parent_rate == 0)
133 parent_rate = parent_rate / (__SHIFTOUT(val, fractional->prediv) + 1);
135 parent_rate = parent_rate / fractional->prediv_val;
156 rate = parent_rate * m;
189 u_int parent_rate, best_rate; local
200 parent_rate = clk_get_rate(clkp_parent)
    [all...]
sunxi_ccu_display.c 105 int parent_rate, best_parent_rate = 0; local
115 parent_rate = clk_round_rate(pllclkp,
117 if (parent_rate == 0)
119 rate = parent_rate * d / m;
125 best_parent_rate = parent_rate;
sunxi_twi.c 85 sunxi_twi_calc_rate(u_int parent_rate, u_int n, u_int m)
87 return parent_rate / (10 * (m + 1) * (1 << n));
91 sunxi_twi_set_clock(struct gttwsi_softc *sc, u_int parent_rate, u_int rate)
101 sunxi_twi_calc_rate(parent_rate, n, m);
sunxi_ccu_nm.c 107 u_int parent_rate, best_rate, best_n, best_m, best_parent; local
138 parent_rate = clk_get_rate(clkp_parent);
139 if (parent_rate == 0)
145 rate = parent_rate / (1 << n) / (m + 1);
147 rate = parent_rate / (n + 1) / (m + 1);
sunxi_ccu_div.c 139 int parent_rate; local
159 parent_rate = clk_get_rate(clkp_parent);
160 if (parent_rate == 0)
163 ratio = howmany(parent_rate, new_rate);
sunxi_rtc.c 525 u_int parent_rate = clk_get_rate(sc->sc_parent_clk); local
529 return parent_rate;
532 parent_rate /= sc->sc_conf->fixed_prescaler;
540 return parent_rate / (prescaler + 1);
sunxi_hdmi.c 848 int parent_rate; local
875 parent_rate = clk_get_rate(clk_pll);
876 KASSERT(parent_rate > 0);
881 int cur_rate = parent_rate / m / d;
892 device_printf(sc->sc_dev, "parent rate: %d\n", parent_rate);
sunxi_hdmiphy.c 374 const u_int parent_rate = clk_get_rate(sc->sc_clk_pll0); local
379 const u_int tmp_rate = parent_rate / (prediv + 1);
  /src/sys/arch/arm/ti/
ti_dpll_clock.c 253 uint64_t parent_rate; local
262 parent_rate = clk_get_rate(clk_parent);
264 return (u_int)((mult * parent_rate) / div);
281 uint64_t parent_rate; local
287 parent_rate = clk_get_rate(clk_parent);
288 if (parent_rate == 0)
291 const u_int div = (parent_rate / 1000000) - 1;
292 const u_int mult = rate / (parent_rate / (div + 1));
323 uint64_t parent_rate; local
329 parent_rate = clk_get_rate(clk_parent)
363 uint64_t parent_rate; local
384 uint64_t parent_rate; local
    [all...]
ti_div_clock.c 169 uint64_t parent_rate; local
202 parent_rate = clk_get_rate(clk_parent);
204 return (u_int)(parent_rate / div);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
gk20a.h 122 u32 parent_rate; member in struct:gk20a_clk
148 clk->parent_rate / KHZ);
nouveau_nvkm_subdev_clk_gk20a.c 99 rate = clk->parent_rate * pll->n;
119 ref_clk_f = clk->parent_rate / KHZ;
518 switch (clk->parent_rate) {
535 clk->parent_rate / KHZ);
634 clk->parent_rate = clk_get_rate(tdev->clk);
641 clk->parent_rate / KHZ);
nouveau_nvkm_subdev_clk_gm20b.c 496 u32 parent_rate = clk->base.parent_rate / KHZ; local
506 nmin = DIV_ROUND_UP(pll->m * clk->base.params->min_vco, parent_rate);
507 nsafe = pll->m * rate / (clk->base.parent_rate);
510 pll->pl = DIV_ROUND_UP(nmin * parent_rate, pll->m * rate);
1054 (clk->base.parent_rate / KHZ));
  /src/sys/arch/riscv/starfive/
jh71x0_clkc.c 253 u_int parent_rate = clk_get_rate(clk_parent);
254 if (parent_rate == 0) {
257 u_int ratio = howmany(parent_rate, new_rate);
325 u_int parent_rate = clk_get_rate(clk_parent);
327 if (parent_rate == 0) {
330 u_int ratio = howmany(parent_rate, new_rate);
442 u_int parent_rate = clk_get_rate(clk_parent);
443 if (parent_rate == 0) {
446 u_int ratio = howmany(parent_rate, new_rate);
  /src/sys/arch/arm/altera/
cycv_clkmgr.c 457 uint32_t parent_rate = 0; local
472 parent_rate = cycv_clkmgr_clock_get_rate(priv, &parent->base);
475 parent_rate /= 2;
477 parent_rate /= 4;
479 parent_rate /= 4;
483 return parent_rate / clk->u.fixed_div;
494 return parent_rate / divisor;
501 return (uint64_t) parent_rate * numer / divisor;
  /src/sys/arch/arm/nvidia/
tegra124_car.c 1216 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); local
1218 return parent_rate / tfixed_div->div;
1244 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); local
1256 rate = parent_rate * 1 / (raw_div + 1);
1264 parent_rate, raw_div);
1266 rate = parent_rate;
1270 rate = tegra124_car_clock_calc_rate_frac_div(parent_rate,
1294 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); local
1305 if (rate == parent_rate) {
1309 raw_div = (parent_rate * 2) / rate - 2
    [all...]
tegra210_car.c 1322 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); local
1324 return parent_rate / tfixed_div->div;
1340 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); local
1352 rate = parent_rate / (raw_div + 1);
1359 rate = parent_rate / ((raw_div / 2) + 1);
1361 rate = parent_rate;
1375 rate = parent_rate / ((raw_div / 2) + 1);
1398 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); local
1409 if (rate == parent_rate) {
1413 raw_div = (parent_rate / rate) * 2
    [all...]
  /src/sys/arch/arm/rockchip/
rk_cru_arm.c 96 const u_int parent_rate = arm_rate->rate / arm_rate->div; local
98 error = clk_set_rate(&main_parent->base, parent_rate);
  /src/sys/arch/arm/samsung/
exynos5410_clock.c 787 const u_int parent_rate = exynos5410_clock_get_rate(sc, clk_parent); local
792 return parent_rate / (div + 1);
807 const u_int parent_rate = exynos5410_clock_get_rate(sc, clk_parent); local
810 tmp_rate = parent_rate / (tmp_div + 1);
exynos5422_clock.c 834 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); local
839 return parent_rate / (div + 1);
854 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); local
857 tmp_rate = parent_rate / (tmp_div + 1);

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